Concurrent Actions in Specman: Part 2
In the previous blog: Concurrent Actions in Specman , we discussed the existing options: all of ( which awaits completion of all branches) and first of (which terminates at the first completion of......
View ArticleIntel at Linley
At the recent Linley Spring Microprocessor Conference, there were two presentations by Intel about deep learning. The first was by Ian Steiner, the lead architect for Cascade Lake. The second was by......
View ArticleVirtuosity: The Top 3 Post-Layout Enhancements in Analog Design Environment
Today's blog highlights the latest enhancements to the post-layout flow. These enhancements address many of the long standing issues, such as mapping schematic and post-layout names, plotting... [[...
View ArticleFree Soloing at VerveCon 2019
No, I didn’t attend VerveCon 2019 alone; there were several Cadence employees there. I’ll explain that title in a minute. Yes, the second annual VerveCon , a conference focusing on cultivating women......
View ArticleFinally, A Certified and Correlated Reference Flow for Advanced Package Designs
As transistor device scaling gets closer and closer to physical limits, more and more companies have been looking beyond silicon and into multi-die approaches with advanced packaging to keep the... [[...
View Article150th Anniversary of the Transcontinental Railroad
150 years ago, technology meant railroads, not semiconductors. I mean, precisely 150 years ago—today is the 150th anniversary of the completion of the transcontinental railroad from Oakland to...
View ArticleHLS Optimizations You Can't Do By Hand
In my previous blog post , I talked about the Quality-of-Results (QoR) that are achievable using High-Level Synthesis tools like Stratus HLS and the fact that exploration of multiple RTLL... [[ Click...
View ArticleBoardSurfers: Look Before You Leap - Verifying Footprints in the Design...
Look before you leap and seeing is believing - two very apt universal truths, and this post is about these truths in a way; about how these truths are related to viewing footprints early in the... [[...
View ArticleSunday Brunch Video for 12th May 2019
https://youtu.be/E61e34IbaRE Made at CDNLuve EMEA (camera Andrea Huse) Monday: Statistical Power...or Why You Shouldn't Be Allowed to Turn Right on Red Tuesday: JasperGold: the Next Generation... [[...
View ArticleBob Smith on ESD Alliance, ES Design West...with Wine
I talked to Bob Smith recently about what's coming up in the world of the ESD Alliance now that it is part of SEMI. One thing that Bob told me is that finally there are baby steps being taken... [[...
View ArticleLIBERATE 19.2 Base Release Now Available
The LIBERATE 19.2 production release is now available for download at Cadence Downloads . For information about supported platforms, compatibility with other Cadence tools, and details of key issues......
View ArticleAfter Meltdown and Spectre
At the recent Linley Spring Microprocessor Conference, the second day's keynote was by Jon Masters of Red Hat. He wears two hats (both of them red) since he is responsible both for their Arm... [[...
View ArticleVirtuosity: Spring-Cleaned Virtuoso Doc Closet
Spring is here and we just got done with our first round of the cleaning action at home over the weekend. Yes, it usually takes us a few weekends to get to the "it-looks-great" feeling! In... [[ Click...
View ArticleWhiteboard Wednesdays - Featuring the new Tensilica Vision Q7 DSP IP for...
In this week’s Whiteboard Wednesdays video, Pulin Desai talks about the latest addition to the Vision DSP family, the Vision Q7 DSP. The Vision Q7 DSP offers up to 1.7X higher TOPS in the same area......
View ArticleVision Q7 DSP: Real-Time Vision and AI at the Edge
At CDNLive EMEA, we announced the latest member of the Tensilica family at the press conference, although it was embargoed until this morning. This is the Tensilica Vision Q7 DSP. The earliest...
View ArticleVirtuosity: Did My Checks Pass or Did They Not Run?
Today's blog highlights Checks/Assert results display and Summary table. This blog is a part of the mini blog series that we are posting twice a week—Tuesday and Thursday—to cover the... [[ Click on...
View ArticleDesigning for the Future - Managing the Impact of Moore's Law
With Moore’s Law, the industry assumes that when you go from one geometry to the next finer node, you will have performance gains. All this is automatic. Chip designers have tried to leverage... [[...
View ArticleSamsung Process Roadmaps
Recently, Samsung held the third Samsung Foundry Forum (SFF) at the Marriott in Santa Clara. They had so many attendees that they pretty much overflowed the biggest ballroom in the hotel and had to......
View ArticleVirtuoso Video Diary: The Next Big Thing — ADE Verifier Teams Up with Cadence...
Today's blog highlights the latest enhancements in ADE Verifier. This blog is a part of the mini blog series that we are posting twice a week—Tuesday and Thursday—to cover the just-released... [[ Click...
View ArticleIC Packagers: Create Daisy Chain Substrates in a Flash with Cadence SiP Layout
How do you go about testing your IC or package substrate when it comes to physical endurance? For many of us, a daisy chain test package is a common option. With practical uses including extreme... [[...
View Article