System in Package, Why Now? Part 2
This post is a continuation of last week's post Multiple Die in Packages. Why Now? That post looked at several of the drivers for system integration increasingly being done using 3D packaging... [[...
View ArticleQuickly View Schematic Designs, Boards, and IC Packages for Free Using...
Do you want to quickly view a schematic, layout, or IC package without installing the complete OrCAD product suite? Get read-only access to design data created in OrCAD Capture , PCB Editor , or... [[...
View ArticleBrian Kernighan's Memoirs
If you have ever worked on placement or floorplanning, and probably some other areas of EDA, then you will have heard of "Kernighan and Lin". It's a partitioning algorithm. You might... [[ Click on the...
View ArticleKnown Good Die
Do you know what known good die are? Do you know what wafer sort is? Final test? Wafer Sort After a wafer has been manufactured in the fab, it usually (but not always) goes through wafer sort. This......
View Article2019 Workshop on Electronic Design Automation in Hsinchu Taiwan
The Cadence Academic Network has been supporting the Workshop on Electronic Design Automation (EDA) in Taiwan since 2016. This year the event was hosted by National Tsing Hua University in Hsinchu...
View ArticleThe Most Important Operating System Ever
I wrote recently about Brian Kernighan's memoir and history in Brian Kernighan's Memoirs . He was at Bell Labs during the most important period for computer science, when the Unix operating... [[ Click...
View ArticleCadence at CES 2020: Tensilica Everywhere
Once again, Cadence will be at CES in Las Vegas. It takes place January 7 to 10, 2020, the start of a new decade. I wonder what electronic marvels we will see before 2030 rolls around. We will be in......
View ArticleDATA Pulse: Speed up ECAD Part Search in Allegro System Capture
You're a designer working on an Allegro System Capture project and you clicked on Place – Add Component some time back, but here's what you've been staring at for a while: You're... [[ Click on the...
View ArticleWhat's Happening in RISC-V Land?
Last week was IEDM, the International Electronic Devices Meeting. I will write about that later this week, because last week was also the RISC-V Summit, which was originally scheduled for the week......
View ArticleIC Packagers: An Introduction to APD+ in 17.4
Some of you are APD users, building single-chip or non-stacked multi-chip packages. Others of you are SiP Layout XL users, probably stacking dies or embedding elements into cavities, whether open or......
View ArticleBoardSurfers: Four Reasons to use Allegro ECAD-MCAD Library Creator
I can bet, right now you are designing the latest smart product, a smartwatch maybe. And, in addition to managing the complexity due to size and density of the product and prioritizing to meet a...
View ArticleSystem in Package? How to Plan and Build It
This is a follow on to my previous two pieces about system-in-package (SiP) designs, System in Package, Why Now? Part 1 and Part 2 . I'm going to use the term SiP generically just to mean any... [[...
View Article2019 Annual HLS Survey Results
Each year, we survey the industry to get an idea of the industry’s experiences and expectations of high-level synthesis (HLS). As in last year’s survey , approximately half of the responses were...
View ArticleIEDM 2019: An Overview...Plus the Future of EUV
IEDM, the International Electron Devices Meeting, took place last week. It was also the RISC-V Summit that week, so I missed most of Tuesday at IEDM since I went down to San Jose. My overview of the......
View ArticleVirtuosity: Looking Back at Virtuoso ADE Product Suite and Virtuoso...
2019 was quite an eventful year for Virtuoso ® ADE Product Suite and Virtuoso ® Visualization and Analysis. We not only added new features such as multi-test editor, but also redesigned... [[ Click on...
View ArticleLibrary Characterization Tidbits: A Matrix for Your Reference
Hi there! Here we are with the last blog for 2019 in the Library Characterization Tidbits series. Keeping it light and just right to match the holiday mood. When working on multiple tools of the... [[...
View ArticleCadence Awards Scholarships to Women Pursuing Technology Education
Building a culture that fosters inclusion and embraces diverse experiences and ideas is fundamental to operating in the modern technology industry. We know that diversity in thought leads to greater......
View ArticleOff-Topic: 2019 TV Anniversaries
It's the day before a holiday. Or in this case, ten days when Cadence will be shut down. As is traditional, I write about whatever I feel like, provided it has nothing to do with EDA or... [[ Click on...
View ArticleCadence Co-organized the First EDA Competition to Help China Train More EDA...
T he first “ China IC and EDA Design Elite Competition ” started i n June 2019 and received high attention and support from many universities. In total, there were 104 teams from 41 universities... [[...
View ArticleSunday Brunch Video for 22nd December 2019
https://youtu.be/iEuzyt_6O_A Made in my living room (camera Carey Guo) Monday: The Most Important Operating System Ever Tuesday: What's Happening in RISC-V Land? Wednesday: System in Package? How... [[...
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