Of Brains and Computers: Keynote by Dr Jan Rabaey
One of the industry’s biggest events, the VLSI Design Conference, took place in Bangalore last week. This conference does a round-robin of cities, and this was the 10th time in its 33-year history......
View ArticleEmerging Memory
SNIA, the Storage Networking Industry Association, organized a webinar recently with industry analysts Tom Coughlin (of Coughlin Associates) and Jim Handy (of Objective Analysis). The webinar was... [[...
View ArticleOff-Topic: Picas, Points, and Printing
Monday is Martin Luther King, Jr Day, and Cadence will be off. Breakfast Bytes will not appear. And so today is the last day before a holiday, and so I write about something off-topic. Today,... [[...
View ArticleA Big Problem with Big Data
I happened to read a blog post that referred to a 2018 paper in The Annals of Applied Statistics with the title Statistical Paradises and Paradoxes in Big Data: Law of Large Populations, Big Data... [[...
View ArticleIC Packagers: Symbol Editing in IC Packages - Choose the Right Option
When you need to edit to a component, even if that is the BGA footprint in need of a pin #1 padstack change for reference of adjustments to the entire bump layout of a flip-chip to feed routability......
View ArticleSunday Brunch Video for 19th January 2020
https://youtu.be/O90mUZyWIeE Made at Lick Observatory (camera Carey Guo) Monday: Details of TSMC's IEDM Presentation on N5 Tuesday: Mark Cuban on Media and AI Wednesday: 5G in 2020 Thursday:... [[...
View ArticleIEDM: Automating DTCO for 3nm
At IEDM in December, Lars Liebmann of TEL presented Design Technology Co-Optimization for 3nm and Beyond . The challenge in designing a modern process is that scaling is no longer based on... [[ Click...
View ArticleDATA Pulse: Simplify Your ECAD Data Release Process While Ensuring Process...
So, who likes sending weekly status reports, filing paperwork, or cleaning the microwave? Zzzz, there's the sound of monotony. What about your ECAD to PLM publishing process? Is that a... [[ Click on...
View ArticleDesignCon 2020: SI, PCB, Packaging, Photonics
Next Tuesday through Thursday, January 28 to 30, DesignCon 2020 takes place in the Santa Clara Convention Center. it is actually their 25th anniversary. I think of DesignCon as being about...
View ArticleBoardSurfers: Leveraging IPC-2581 Spec Element Capabilities to Streamline...
If you are a PCB designer and follow IPC-2581 guidelines to design a board, this solution is for you! To ensure on-time and quality fabrication, it is essential that your design team conveys the... [[...
View ArticleIEDM: TSMC on 3nm Device Options
At IEDM in December, Jin Cai of TSMC presented Device Technology for 3nm Node and Beyond during the short course on Sunday. He divided his presentation up into four parts: Historical CMOS scaling... [[...
View ArticleRIP Clayton Christensen
Clayton Christensen died last Thursday, at the relatively young age of 67. He was the author of what I think is the best book on strategy for high-tech organizations, The Innovator's Dilemma . I... [[...
View ArticleIEDM: Novel Interconnect Techniques Beyond 3nm
During the short course on the Sunday before IEDM, Chris Wilson of imec presented Novel Interconnect Techniques for Advanced Devices Beyond 3nm . In some ways, this is a complementary presentation...
View ArticleIC Packagers: Mysteries Revealed - Why is Flip-Chip Chip-Down the Default...
We’ve come to the end of my New Year’s Resolutions for 2020 . Before we dive deeper into the exciting new capabilities to be found in the 17.4 release , though, I’d like to address a question I hear......
View ArticleSigrity Aurora: In-Design Analysis
Cadence's new Sigrity Aurora puts all the power of the Sigrity engines under the Allegro user experience. The new capability allows a team to go from preliminary exploration, through design, to... [[...
View ArticleQuarry Bank Mill: A Technology Museum from the Industrial Revolution
A couple of years ago (and from time to time since) I wrote a series of blog posts about technology museums. Here are the links: The Intel Museum German Computer Museums British Computer Museums The......
View ArticlePersistent Memory: We Have Cleared the Tower
Last week it was the Persistent Memory Summit 2020, which has been running annually since 2013. Jim Pappas gave the state of the union address to open the summit. Back in 2017, he used a space... [[...
View ArticleUSB3, PCIe, DisplayPort Protocol Traffic Finding its Way Through USB4 Routers
USB4 can simultaneously tunnel USB3, PCIe and DisplayPort native protocol traffic through a hierarchy of USB4 routers. The key to tunneling of these protocols is routing table programmed at each... [[...
View ArticlePersistent Memory at Twitter
A couple of weeks ago was the Persistent Memory Summit 2020. See my post Persistent Memory: We Have Cleared the Tower for an overview. This week I am going to cover two presentations, one from... [[...
View ArticleHow Technologies Get into EDA
When I was last at Cadence around 2000, I ran what was then Custom IC. It was a different grouping from what we call CPD today, I had physical verification (remember Dracula? Vampire? Assura? Diva?)......
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