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Keynote: From “Tribulations” to Mixed-Signal Success at Texas Instruments
Texas Instruments has experienced many "tribulations" in mixed analog and digital design, according to Chris Collins, director of TI's Analog Division. But significant progress is underway. At a...
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Panel: Mixed-Signal Designers Reveal “Gaps” and Solutions
Are we closing the gaps in mixed-signal design? That question was posed to five panelists, including three Cadence customer representatives, at the Mixed-Signal Technology Summit held at Cadence Sept....
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PCB West Update: How IPC-2581 Data Transfer Standard is Moving Forward
Last year the PCB West conference held a lively panel discussion about data transfer formats for PCB design and manufacturing. Most panelists and many audience members were enthusiastic about IPC-2581,...
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What's Good About PCB SI Static IR Drop Analysis? 16.5 Has Many New...
In the Allegro PCB SI 16.5 release, static IR drop analysis has been integrated into PDN (power delivery network) analysis, with several new features added, such as current density display and the...
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Webinar: Is SystemVerilog the Future of Mixed-Signal Modeling?
Real number modeling (RNM) provides a fast way to run a chip-level simulation with analog values, but support for it in the current SystemVerilog Language Reference Manual (2009 LRM) is very limited. A...
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Q&A: Phil Bishop, New Cadence VP, Drives Adoption of System-Level Design
Phil Bishop has come into his new role - Vice President and General Manager of System Level Design at Cadence - at an exciting time. After years of slow growth, technologies such as high-level...
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Interconnect Workbench Eases Analysis and Verification for ARM-Based SoCs
In today's complex SoCs, early performance analysis and verification of SoC interconnect is crucial. Architects must ensure that interconnect will meet the bandwidth and latency requirements of the...
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What's Good About DEHDL’s Page Search? The Secret's in the 16.5 Release!
Prior to the 16.5 release, the search capabilities in Allegro Design Entry HDL (DEHDL) have been quite limited. This has changed in the 16.5 release with the introduction of a new toolbar for page...
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Customer Support Recommended – Working with PADS to Allegro PCB Editor...
A recently published AppNote on converting a PADS ASCII file to Allegro PCB Editor has eased the life of many users by providing a step-by-step methodology and appropriate debugging techniques. It also...
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Recorded Webinar: Using Metric-Driven Verification and Formal Together For...
[Preface: the upcoming "Club Formal" on October 17 here at the Cadence San Jose campus will also touch on this topic - please join us!]While it's now common knowledge that there are many benefits to...
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Using pli_access for Stubless Indexed Ports
Indexed ports are used to access composite HDL objects in SystemVerilog (SV). Their most frequent use is to access SV multi-dimensional arrays by defining a simple indexed port and accessing the array...
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UVM SystemVerilog in a Multi-Language SoC World: UVM-ML Webinar
Every SoC project uses multiple languages. Even if the design itself is purely Verilog RTL, it's likely that you have some PLI-based stimulus. In many cases there are multiple languages in use due to...
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Your First Low-power Verification Project - Webinar
So your team just specified its first design with power management circuits. The designers are telling you, its just a few power shut-off domains defined by CPF or UPF. The verification should be...
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Si2: Jim Hogan Predicts “Custom 2.0” IC Design Retooling
Are we heading for a major retooling in custom IC design? EDA veteran Jim Hogan thinks so, and in a keynote speech at the Silicon Integration Initiative (Si2) Conference Oct. 9, 2012, he argued that...
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Five-Minute Tutorial: Why You Should Be Running Early DRC
Everyone knows you have to run signoff DRC before you tape out a design. Sometimes, DRC is left to exactly that moment - right before the tapeout. If major problems are found in the design at that...
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Changing the Game with Processor Based Emulation
I have always been fascinated by game changing moves. Some are more successful than others, but the general principle is always the same - coming with a gun to a knife fight. Two of my favorites are...
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Si2 Talk: Why System-Level Low Power is Challenging
There's a lot of interest in "system level" low power design -- but what does it really mean? "There a lot of confusion," said Pete Hardee, director of solutions marketing at Cadence, in a presentation...
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SKILL for the Skilled: Many Ways to Sum a List (Part 4)
In the previous posts SKILL for the Skilled: Many Ways to Sum a List (Parts 1, 2, and 3) we looked at several ways to sum a given list of numbers. We ignored the cases of the given list being very...
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What's Good About ADW’s Multiple Shopping Lists? Check out the 16.5 Release...
The 16.5 Allegro Design Workbench (ADW) now supports multiple shopping lists.In a nutshell, multiple shopping lists support these capabilities: • Provide viewing multiple lists from: – One or...
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A New Information Resource for 3D-IC TSV Design
A new solutions page on Cadence.com provides a great deal of information about 3D-ICs with through-silicon vias (TSVs). In addition to a description of the Cadence 3D-IC design, test, and semiconductor...
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