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Virtuosity: 12 Things I Learned in October by Browsing Cadence Online Support
Lots of routing, a little AMS, and finishing off with some fun...Application Notes1. Constraint Implementation and Validation in interoperability flowThe Mixed Signal Interoperability (MSI) flow allows...
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User View: UVM Sequence Layering Brings IC Functional Verification to Higher...
Engineers at a leading IC design services company recently came up with a novel approach that improves verification efficiency by "layering" sequences of transactions to reach higher levels of...
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Signal Integrity Analysis of Serial Data Channels—A Complete Solution Using...
Back in the day, when challenged to transfer data faster, we increased the width of the interface from 8 bits to 16 or from 16 to 32 and so on. The wider the bus got, the more challenging timing...
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Hardware/Software Modeling Opportunities and Strange Beasts
SAN JOSE, Calif.—Ever seen an Eierlegende Wollmilchsau? If you have, you're sitting on an electronics design automation gold mine.That was the question Cadence's Frank Schirrmeister posed Monday to a...
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High-Level Synthesis Now Spans the Datapath-Control Spectrum
When we talk to prospective high-level synthesis (HLS) customers, one of the slides we show is a pie chart that breaks down the types of production designs (that we are aware of) for which customers...
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Digital Cameras to Get New Image Sensor Technology
Fifteen years ago (at least!) we bought an HP laptop for our home and they generously threw in a digital camera. That was the first digital camera we ever had. What a revelation it was to take pictures...
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ICCAD Keynote: Will Resolution-Challenged Lithography Improve IC Design?
First, the bad news. We may have to go all the way to the 7nm process node without extreme ultraviolet (EUV) lithography, using increasingly clever tricks—and restrictions and constraints—so our...
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SKILL for the Skilled: Simple Testing Macros
In this post I want to look at an easy way to write simple self-testing code. This includes using the SKILL built-in assert macro and a few other macros which you can derive from it.The assert macro...
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Low-Power IEEE 1801 / UPF Simulation Rapid Adoption Kit Now Available
v\:* {behavior:url(#default#VML);} o\:* {behavior:url(#default#VML);} w\:* {behavior:url(#default#VML);} .shape {behavior:url(#default#VML);} 0 0 1 644 3674 Cadence Design Systems 30 8 4310 14.0 Normal...
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Optimize Your PCB Decoupling Capacitors and Remain a Person of Integrity
How much integrity is too much? If your PCB designs apply one or more decoupling capacitors (decaps) per power pin, then you may have too much integrity - power integrity, that is. Your designs are...
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Accelerating Code Coverage Using Palladium XP Rapid Adoption Kit
Code coverage is an effective tool in the verification process, giving insights into testing completeness as well as identifying highly active or inactive areas of a design. Collecting code coverage in...
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Signoff Summit: An Update on OCV, AOCV, SOCV, and Statistical Timing
It's easy to be confused by the alphabet soup of acronyms that surrounds static timing analysis (STA). At the Signoff Summit at Cadence headquarters on Nov. 21, 2013, Igor Keller, senior R&D...
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ICCAD 2013: The New Electrically Aware Design Paradigm
SAN JOSE, Calf.--Pop quiz: What percentage of verification time do design teams spend on re-iterating their layout design after checking electrical parameters?If you said 30-40 percent, move to the...
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SKILL for the Skilled: SKILL++ hi App Forms
One way to learn how to use the SKILL++ Object System is by extending an application which already exists. Once you understand how extension by inheritance works, it will be easier to implement SKILL++...
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Covering Edges (Part I) – Cool Automation
With random generation, most of the fields are due to be quite well covered. If the field is of a type with a wide space, e.g. address is of 32 bits, then most likely not each and every of the...
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What's Good About AMS Multi-Core Engine Support? It’s in the 16.6 Release!
The 16.6 AMS Simulator (PSpice) release now includes support for multi-core capabilities. There are several runtime options available to enhance the performance of simulation runs.Read on for more...
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Signoff Summit: Tempus, Path-Based Analysis, and FinFET Timing Closure
The recent Cadence Signoff Summit produced a wealth of information about the technology behind the Tempus Timing Signoff Solution, as well as some deep background about current challenges in static...
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Great Progress with Ethernet Standards Development
The IEEE 802 local area networking standards committee held its plenary meeting in Dallas recently at the Hyatt Regency Hotel. As a historical side, here is a photograph of the Hyatt from Dealey Plaza,...
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Amazon Prime Air and the Eeyore Backlash
There was Amazon founder Jeff Bezos, doing it again, with a big smile, an easy laugh and another great idea. This time it was on "60 Minutes," and he surprised interviewer Charlie Rose with the...
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Q&A: Phil Moorby, Verilog Inventor and Cadence Fellow, Sees a Parallel Future
Few people have influenced the EDA industry as much as Phil Moorby, inventor of the Verilog hardware description language (HDL) and the first Verilog simulator. As Cadence celebrates its 25th...
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