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New MMSIM 12.1: How to Set up Transient and Harmonic Balance Analyses with...
Preview of Coming Attractions! Here's a new method that will save you simulation time in MMSIM12.1. (Be sure to use IC615 ISR14 or later to see the new MMSIM12.1 features in the GUI.) Here is the...
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Function Level C Interface – New C Interface for Specman
Working with the conventional Specman C language interface has two major disadvantages:1. There is a tight dependency between the e code and the C code. The user must include the Specman header...
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How Cadence Helps Universities Build EDA Infrastructures
Many EDA companies, including Cadence, have university programs that make it easier for academia to acquire tools. But what about the software/hardware infrastructure that supports those tools? In this...
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Alberto Sangiovanni-Vincentelli at ICCAD: From Early EDA to the "Sensory Swarm"
Few people have been as influential in the development of EDA as Alberto Sangiovanni-Vincentelli, professor at the University of California at Berkeley and Cadence board member. At the International...
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Archived Webinar: Variation-Aware Analysis for Advanced Node Design
Why is variation such a big problem at 45nm and below, and what can custom/analog designers do to analyze and mitigate it? A new series of Cadence webinars on "variation-aware design" helps answer...
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MMSIM12.1 SpectreRF Preview of Coming Attractions! - Part 1
Greetings! MMSIM 12.1 contains many new features to aid RF designers. Here's a preview of the changes... Documentation Improvements The SpectreRF User Guide is being completely rewritten and updated...
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Transitioning Your LEF-Based EDI System Design Flow to OpenAccess
The trend of combining analog and digital circuits on a single chip has been growing for several years. More recently I'm seeing more and more designers improve their productivity by transitioning...
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What's Good About APD’s Shape Shorting? You’ll Need the 16.6 Release to See!
In some designsflows, you need to connect two plane shapes on the same net, but on different layers, together with vias in order to improve connectivity. These “shorting” vias are placed in a regular...
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Whitepaper: New Methodology Needed for 20nm Custom/Analog IC Design
Before digital SoC designers take advantage of the power, performance and density advantages of 20nm, custom/analog designers must develop the standard cells and the analog/mixed-signal IP. Thus, no...
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CDNLive paper: High-level Synthesis on Video Processing ASIC
The proceedings from the recent CDNLive! event in Israel recently became available, and you can access them with your Cadence.com account login. The paper entitled "High-level Synthesis on Video...
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Cadence Has Significant Presence in ARM TechCon 2012 and Worldwide ARM...
The recently concluded ARM TechCon 2012, the annual event for ARM users (including hardware and software engineers) along with ARM ecosystem partners, was a huge success. Once again, this event...
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Bill Beausoleil, 1950s Computer Pioneer, Shapes RTL Emulation Technology Today
An important aspect of any advanced technology -- including the RTL emulation systems used for IC verification - is the expertise that stands behind it. Few can claim more expertise than Bill...
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Discussing Mixed Signal -- New On-Line Forum, and 3-Day Training Classes
Are you working in the area of mixed signal?Then you may want to exchange information and experiences with other engineers. At the Cadence Community, a new Mixed-Signal Design Forum has been launched,...
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The Case for the Tiny Testcase
I often joke with customers that, although I realize they have to work on large designs, I do my best work on designs with just 2 or 3 instances. That's because I'm often trying to replicate an issue...
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Need e/Specman Expertise ASAP? Free Training and Verification Alliance...
Recently an EDA industry observer relayed some Specmaniacs' concerns about satisfying the increasing demand for e/Specman trained verification engineers in Europe and other geographies. Team Specman...
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MMSIM 12.1 SpectreRF -- Preview of Coming nport Attractions! Part 2
Greetings, MMSIM 12.1 contains many new features to aid RF designers. Many of these changes are described in my Part 1 blog post. I've saved my favorite for last....here's a preview of the changes to...
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Optimizing ARM Based Designs for Low Power using Emulation
The month November goes to the Brits, no question. Not only did the James Bond movie Skyfall open, but Santa Clara also experienced somewhat of a "British Invasion" for ARM TechCon in the Santa Clara...
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Is Fast SPICE Simulation Hitting a Wall?
The transistor-level SPICE simulator has been the gold standard for custom/analog verification for decades. But SPICE is too slow for many applications in which transistor-level accuracy is needed....
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UVM e vr_ad -- Specman Read/Write Register Enhancements
If you are a Specman vr_ad user, you probably know that register access is implemented using the read_reg / write_reg. For reading/writing a register, you have to 1. Extend a vr_ad_sequence2. Add a...
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Cadence Partner Udacity Brings Higher Education to the World
On-line education pioneer Udacity is partnering with Cadence to offer an upcoming free class in functional hardware verification - but Udacity's overall mission is quite a bit broader than that. Says...
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