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AdaptIP Talk About Their High-Level Synthesis Approach at CDNLive
At this year's CDNLive, AdaptIP presented their experiences with high-level synthesis (HLS), in particular Cadence's Stratus HLS product. The presenter was billed as being Farhad Mighani but he...
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Q&A: Dr. Ziyad Hanna on Emerging Needs in Formal Verification and His Oxford...
Dr. Ziyad Hanna, a Cadence VP of R&D in formal and automated verification, was recently appointed a visiting professor at the Department of Computer Science at the University of Oxford, England....
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Announcement of MEMS Design Contest at DATE
On March 17 th in the Exhibition Theatre at DATE, there was the first public announcement of the worldwide MEMS Design Contest. The organizers Cadence, Coventor, and X-FAB provided an overview of the...
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Jim Hogan and the Early Days of Virtuoso
I had lunch with Jim last week to get a little color on the early days of the Virtuoso platform. As you probably know, those days were 25 years ago, as this year is the 25th anniversary of the Virtuoso...
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CDNLive Keynote: Expanding Your Opportunities with System Design Enablement
In the not-too-distant future, major city centers might operate fleets of autonomous vehicles to transport residents from point A to point B. People would have less need for car ownership, traffic...
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Cadence Online Support – Empowering Learning! New learnings - February,...
Cadence Online Support Features “ Most Popular ”: This section displays content items basis your “search” and technology platform selections. Use My Support - What's New to explore the new features of...
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Modelling a Value Holder Template with the Value “new-ed” by Default
In many companies, there is a well-defined flow for handling monitored data items: match the input data to output data (or, match a response to a request), update data, for example latency or the time...
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Qualcomm Looks to the Future: Steve Mollenkopf's CDNLive Keynote
Steve Mollenkopf, the CEO of Qualcomm Incorporated, gave one of the keynotes at CDNLive here in Silicon Valley. Just a little background in case you know little about Qualcomm. They started in...
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What's Good About the latest RF PCB? New capabilities in 16.6-2015!
The 16.6-2015 RF PCB release contains many new features and updates. Read on for more details … Allegro Discrete Library to ADS Translator Enhancements This release includes several enhancements in...
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Cadence Participates in 14 Spring Career Fairs
Rain or snow does not stop our Cadence employees from being the perfect brand ambassadors. Check out the picture below! From early January to late February, Cadence attended 14 career fairs across the...
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Whiteboard Wednesdays - Common Infrastructure Between Simulation VIP and...
In this week's Whiteboard Wednesdays video, Arindam Guha discusses the common infrastructure between Verification IP and Accelerated Verification IP and how it assists in making the migration between...
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Academic Track Makes Its Debut at CDNLive Silicon Valley
For the first time at CDNLive Silicon Valley, Cadence Academic Network hosted an Academic Track where seven professors from leading North American universities shared their outstanding work in research...
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CDNLive Silicon Valley 2016—The Bigger Picture
When a presentation makes us think about an industry on a whole new level and rethink potential outcomes for something significant in our lives, it’s a huge success. Like a TED presentation. This...
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TI and UI: Texas Instruments' Experience with the Common User Interface
Cadence's tools Genus, Innovus, and Tempus have a lot of functionality in common. For example, they all contain the same timing engine, and a database, and constraints. One thing that they don't have...
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Memory, the Turning Point of Chinese Semiconductor Industry
I can't keep away from work. Saturday found me in the Cadence auditorium for the quarterly meeting of CASPA, the Chinese-American Semiconductor Professionals Association. Yes, I have noticed that I am...
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RTL Signoff vs. Functional Signoff
The notion of signoff has many layers to it, both in terms of complexity but also in terms of meaning. In my last blog post, I talked about some of the imprecise attributes of functional verification,...
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Memory in China: XMC
Yesterday I covered the first half of the CASPA meeting last Saturday about memory in China. That was the big picture. Simon Yang, XMC The meeting actually opened with Simon Yang, the CEO of XMC,...
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"Interoperability is the Only Way to Prove Standards Compliance"
At the recent TSMC Technology Symposium, Cadence and Mellanox demonstrated multi-lane interoperability between Mellanox’s physical interface (PHY) IP for PCIe 4.0 technology and Cadence’s 16Gbps...
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Built on a Rich History: 25 Years of Virtuoso Analog Design Technology
As Cadence celebrates 25 years of its Virtuoso Analog Design Environment (ADE), the company has also announced its next-generation platform, which promises an average of 10X performance and capacity...
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Building Efficient Scoreboards
A “scoreboard” is a verification component that checks the data sent to the DUT against the data received from the DUT. The fundamental flow of the scoreboard is simple: Items sent to the DUT are added...
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