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Why C-to-Silicon Compiler HLS has Supported IEEE 1666-2011 SystemC All Along
Recently one of our competitors issued a press release claiming to be the first high-level synthesis (HLS) vendor to support IEEE 1666 TM -2011 SystemC. Specifically mentioned was newly-added support...
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DVCon 2013 Lunch Panel: Best Practices in Verification Planning
While standardized methodologies guide many other aspects of functional verification, planning the verification process is as much an art as a science. How can you know if you're following "best...
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Virtuosity: 10 Things I Learned In January By Browsing Cadence Online Support
This month's highlighted content includes helpful information on wreal modeling, mixed-signal interoperability, verification of digitally-calibrated analog circuits, device and block-level routing and...
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Whitepaper Review: Improving Gate-Level Simulation Performance
As I wrote in a January 2013 blog post, a recent Cadence customer survey confirmed that gate-level simulation usage is increasing, and that it can potentially take up to one-third of the simulation...
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It’s Coming: Udacity CS348 Functional Hardware Verification Course Launches...
On October 18, 2012 Google, NVIDIA, Microsoft, Autodesk, Cadence and Wolfram announced their collaboration with Udacity. Working with Udacity, each of the companies listed above is developing new...
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What's Good About OrCAD Capture’s Signal Integrity Flow? The Secret's in the...
With the 16.6 release, you now have the capability of utilizing the PCB SI tools (SigXP) to work with topologies and constraints in the OrCAD Capture environment.Capturing constraints early in design...
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Planning to Go to DVCon 2013 Next Week? If So, Don't Miss the Debug Tutorial...
TUTORIAL: Fast Track Your UVM Debug Productivity with Simulation and AccelerationSession: 5T on Thursday, Feb. 28th from 8:30AM - 12:00PMFor more details on the debug tutorial, click hereThis debug...
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What the 787 Dreamliner Can Teach Us About SoC design
The commercial aircraft industry is at a stage where it innovates at a much slower pace than the chip design industry -- however, we can find some parallels that offer us lessons. The most notably...
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New Book: Analog Design and Simulation Using OrCAD Capture and PSpice
Thousands of engineers worldwide use OrCAD Capture for PCB schematic entry and PSpice for circuit simulation. These popular products, both provided by Cadence, deserve a good "how to" book -- and now...
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Five-Minute Tutorial: Create Encounter Power System (EPS) Power-Grid Views...
In today's tutorial, I'm giving you a sample EPS (Encounter Power System) script that you can use to generate power-grid views for your standard cells. Power-grid views are used during rail analysis,...
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Embedded World 2013: Virtual Platforms Connected to Everything
Sometimes it is hard to explain why certain ideas take off and why others don’t. There are many stories of poor products that are more successful than much better products. There are also many stories...
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Application Specific System-Design and Verification at Embedded World and DVCon
This week (February 25 th 2013) is a busy one for system development and the Cadence System Development Suite in particular. For mobility, the place to be is Barcelona -- the Mobile World Congress will...
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"Smart Devices" and How They Affect Your Mixed-Signal SOC Verification
We are seeing a huge trend -- the mobile revolution is changing the way we go about our everyday lives. Gone are the days where the term 'Internet' was associated with a PC or Mac. The smartphone...
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DVCon 2013: Engineers Question EDA Standards Leaders at Accellera “Town Hall”...
Do design and verification engineers care about EDA standards? If the Accellera Systems Initiative"Town Hall" meeting at DVCon 2013 Feb. 25 is any indication, the answer is an emphatic yes. A packed...
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What's Good About Allegro AMS New Advanced Options? They’re in the 16.6 Release!
The Allegro AMS Simulator (analog/mixed-signal) 16.6 release adds several enhancements to the Advanced Options dialog form. This enables the customizability of a PSpice simulation run, including...
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Archived Webinar: SuperSpeed USB 3.0, Verification Challenges, and Solutions
The growing adoption of SuperSpeed USB (USB 3.0) is enabling some exciting new product designs, but it's also causing a big functional verification challenge. A recently archived Cadence webinar...
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Securing Invisible Things … or “Why Denial Works!”
The opening keynote of the Embedded World conference in Germany left me with chills. No, it was not a grand theatrical performance letting me crave for more. It simply scared the bejevies out of me...
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Remove Die Stack Layers from NC Drill Outputs using Cadence 16.6 SiP and APD...
As we continue with our series on improvements to the manufacturing and documentation outputs in the Cadence 16.6 IC Packaging layout tools, our focus this week is on NC Drill outputs. For as long as...
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DVCon 2013 Panel: 1 Million IC Design Starts – How Can We Get There?
If you want to organize an interesting panel discussion, think big - really big. J.L. Gray, vice president of Verilab and author of the Cool Verification blog, did just that with a DVCon 2013 panel,...
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What's Good About Allegro PCB Editor Place Replicate Text Support? Check Out...
The Allegro PCB Editor Place Replicate application now supports the processing of component reference designators. The work performed in customizing assembly text or silkscreen to the seed circuit can...
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