Hybrid Memory Cube (HMC) is a memory architecture that was developed by Micron in 2011. It was developed in response to the high-bandwidth, high-efficiency memory requirements of multi-core processing in supercomputing and advanced network systems. HMC represents a fundamental and key change in how memory is used in the system. By placing intelligent memory on the same substrate as the processing unit, each part of the system can do what it's designed to do far more optimally than any previous technology. Every HMC memory chip has a small, high-speed logic layer that sits below vertical stacks of DRAM die that are connected using through-silicon-via (TSV) interconnects. The DRAM has been designed to handle data exclusively, with the logic layer handling all DRAM control within the HMC. The energy-optimized DRAM array provides efficient access to memory bits via the logic layer, providing an intelligent memory device truly optimized for performance and energy efficiencies. HMC is now enjoying some renewed interest due to the recent developments in extreme networking. Extreme networking refers to a class of Ethernet switches and routers that are ultra-high performance networking solutions, and typically involves advanced security. Advanced security features require high bandwidth, minimal latency, and large data sets for use in functions like table lookups, address translation tables, etc. HMC provides the higher performance through improved latency and higher bandwidth to meet those demands. HMC has reduced latencies, due to the greater number of responders built into HMC, resulting in lower queue delays and higher bank availability. A single HMC unit can also provide more than 15X the bandwidth of a DDR3 module due to the dense interconnects and shorter path lengths that the unique stacked architecture allows for. Cadence memory model is the de-facto industry standard for HMC memories. Cadence has had HMC VIP in production since August 2011 and its support for HMC VIP includes multiple generations of the specification, from pre-1.0 to HMC 2.1. In addition to HMC, Cadence also has an extensive portfolio for other high-speed memories such as DDR3, DDR4, DDR4 3DS, HBM, and Wide I/O 2, with multiple customers using all these high-speed memory models and support for these models from multiple vendors. In addition, Cadence offers a state-of-the-art next-generation protocol debug aid for memories called Indago Protocol Debug. Cadence IP and memory models provide many advanced capabilities, such as: Support for any language, any methodology, and any simulator Full access, control, and debug capabilities for all memory transactions and contents Library routines with back-door writes and memory callbacks Error injection via call backs and register access Extensive protocol and error checks Priya Balasubramanian![]()
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