PCI-SIG Developers Conference 2016 is now history, taking place at the Santa Clara Convention Center at 28 th -29 th June, once again proving it’s not an event you want to miss. With PCIe 4.0 standard maturing, we’re seeing a lot of action in the market, though there are questions that have to be answered. There were questions about PCIe 5.0, and though it will become an important project, the SIG wisely is staying focused on finishing PCIe 4.0. From the PR session we know PCIe 5.0 will be 32 GT/s, with specifications appearing in 2017. As reported in EE Times , “it’s been more than six years since the PCI SIG ratified its last major standard, the 8 GT/s PCIe 3.0”. Back to the present, Cadence showed 4 demos on PCI-SIG, spanning both verification and design IP, pre-silicon protocol debugging, and PCIe 3.0 and 4.0, including interoperability of the PCIe 4.0 PHY with Mellanox. Figure 1 – PCIe Indago Debug Platform demo with Verification IP Figure 2 – PCIe Gen 4.0 Controller demo Figure 3 – PCIe Gen 4.0 PHY Interoperability with Mellanox demo Figure 4 – PCIe Gen 3.0 Controller and PHY demo![]()
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