As I mentioned in my last blog post , portable stimulus is one of the main areas of focus for me at Cadence. Paul McLellan has published two excellent posts about Perspec System Verifier, our product offering in the space, but for today I’d like to take a step back and talk about the concept of portable stimulus and its promise for the industry. To be clear, I am speaking for myself and not in any official capacity for Accellera or the Portable Stimulus Working Group (PSWG). Three key goals lie at the heart of portable stimulus and the Accellera PSWG vision for a portable stimulus standard: improved verification reuse, test creation automation, and improved coverage. To a large extent these same goals could be said to apply to the existing Universal Verification Methodology (UVM) standard. Therefore, we should start by reviewing the status of the UVM and discussing both its virtues and its limitations. The UVM has been a huge success by almost any measure. Drawing on pre-existing verification methodologies from the three major EDA vendors, it added in the experience of expert users to offer a standardized way to perform constrained-random simulation. Nearly everyone with a SystemVerilog testbench has adopted the UVM, and there are also SystemC and e flavors available for verification teams who prefer those languages. The UVM automates the creation of transactions and sequences in a simulation testbench and, because of its randomization, covers more aspects of a design than manual tests would do. It also supports some forms of reuse. It allows testbench components to be shared among projects and enabled the establishment of a commercial verification IP (VIP) industry. Also, it can be extended beyond pure software simulation into simulation acceleration. However, the UVM does not extend to in-circuit emulation (ICE), FPGA prototypes, or silicon in the bring-up lab since these platforms do not use simulation-based testbenches. Further, reuse of UVM testbench components from the IP level to the full chip is limited. Passive elements such as protocol monitors and scoreboards may be reusable, but sequencers and results checkers usually must be rewritten. It’s not possible to simply plug together the verification components from all the IP blocks to verify a higher-level subsystem or system. Finally, the UVM does not encompass system-on-chip (SoC) designs where verification tests are running in the embedded processors. SoCs are generally best verified with software-driven techniques that leverage the power of the processors. None of these points should be taken as a criticism of the UVM; it does what it was designed to do. However, evolution in the industry caused verification engineers to think about what would come next. This is exactly where portable stimulus comes in. As shown in the diagram below, the Accellera vision is that tests can be automatically generated from an abstract model of verification intent. These tests include stimulus, results checks, and coverage metrics. Neither the stimulus nor the tests are truly portable; the model is portable in the sense that it can be used to generate tests tuned for IP blocks, subsystems, or full systems in simulation. These tests can also be generated for all verification engines, from virtual platforms to silicon. Note that the generated tests include software running on the embedded processors and, when necessary, coordination with the SoC’s inputs and outputs. Much as the UVM eliminated the need to hand-write transactions and sequences in the testbench, portable stimulus eliminates the need to hand-write system-level tests for any verification platform. The generated tests represent use-case scenarios more complex and with better coverage than could be written by hand even if time permitted. Portable stimulus improves verification reuse since the abstract models for IP blocks can be combined directly into a model for a higher level in the design hierarchy. The model for a complete SoC, or even a multi-SoC system, can be constructed this way. Tests at every level and for every platform can be generated automatically, increasing verification efficiency by at least a factor of ten, and sometimes considerably more. Finally, the complexity of these tests yields much higher system-level coverage than can be achieved by other methods. Indeed, Accellera has a broad vision, but it represents the state of the art in verification. Perspec System Verifier delivers on this vision today, and we are leveraging our extensive experience in this space to help the Accellera PSWG develop the best possible standard. Of course, we are fully committed to supporting the standard when it is ready. In future posts, I will talk more about the emerging standard as well as how we enable our customers to use portable stimulus successfully today. Please join me on this journey. Tom A. The truth is out there...sometimes it's in a blog.![]()
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