DVCon Europe in Munich is coming up on 19 and 20 October. For any Americans reading this and thinking October in Munich means Oktoberfest and beer, I hate to disappoint you. Despite the name, Oktoberfest is largely in September (it ends on the first Sunday in October). The first day of DVCon Europe, there is a keynote and the rest of the day is taken up with tutorials, then another keynote during the dinner. The second day has a keynote and the rest of the day is taken up with papers. Wednesday, 19 October The opening keynote is by Hobson Bullman of ARM, titled Design and Verification Focus in ARM TSG . OK, I had to look it up too. TSG is the Technology Services Group, where Hobson is the general manager. The end of the abstract seems to sum up what he will be talking about: In this keynote, Hobson will address some of the methodology and infrastructure challenges faced, and solutions delivered by TSG, for delivering IP into a demanding partner base, across a wide variety of markets. There are then two Cadence tutorials. They are in parallel so it is not possible for anyone (me) to attend both of them. The first is about the Accellera portable stimulus working group (PSWG), How Portable Stimulus Addresses Key Verification, Test Reuse, and Portability Challenge . The tutorial is organized by Cadence with Larry Melling of Cadence, Staffan Berg of Mentor, Adnan Hamid of Breker, Adiel Khan of Synopsys, and Karthick Gururaj of Vayavya. These are the companies that are involved in the working group defining the standard. If you don't know much about the standard, then this is your opportunity to find out. The other is in the automotive space, ISO 26262 - This Changes Everything , presented by Riccardo Oddone, Matt Graham, and Viktor Preis, all of Cadence. ISO 26262 is the functional safety standard for electronics in automobiles. This level of reliability and functional safety is new for most of the semiconductor, IP, and EDA industries, which have been driven in recent years by mobile (and before that PC), which doesn't have the extended temperature range, long lifetime requirement, or the possibility of life-threatening failures. Later that afternoon, Larry Melling is back with Sharon Rosenberg, talking about Model-Driven Approach to Software-Driven Verification . One sentence in the abstract is: With today’s SoCs including more cores, more IP, complex power control, coherent interconnect, and complex software controlled operations, software-driven verification is essential to verifying SoC features, but it introduces unique challenges in terms of writing tests for complex interactions at the subsystem and SoC level. Hmm, that sounds like the value proposition of Cadence's Perspec System Verifier. This is powerful technology with which we have been engaging with a limited number of customers. If you have never heard of it, then this is really part 2 of the portable stimulus tutorial from the morning. In the evening the exhibition is open from 5.30pm to 7.30pm. Then, during (or probably after) the dinner, Lucio Lanza of Lanza Ventures gives the dinner keynote, Supporting the Exponential Growth in New Application Areas . If you have heard Lucio talk in recent years, you know that he is convinced that there is more to semiconductor design than the most bleeding-edge process nodes. As he says: The biggest challenge to semiconductor companies will evolve from supporting more advanced, leading-edge SoCs to extending their viability to support a variety of creative designs in unique application areas stretching process nodes in new ways. Thursday, 20 October The Thursday keynote that opens the day is by Jürgen Weyer of NXP, where he is the VP of automotive sales for EMEA. His paper is titled The Road Ahead for the Securely Connected, Self-Driving Car . He will talk about CMOS radar, V2V, V2I, sensor fusion, and gigabit Ethernet, among other things. Later in the day, NXP and Cadence are on together to present Enhancements of Metric-Driven Verification for ISO 26262 . This is a follow-on, in some ways, from the preceding day's tutorial. The authors are Michael Rohleder, Clemens Roettgermann, Stephan Ruettiger, all of NXP along with John Brennan, Matt Graham, and Riccardo Oddone, all of Cadence. Gagandeep Singh of Cadence is the author of Addressing Renewed Gate-Level Simulation Needs for 10nm–28nm and Below . The exhibition is open all afternoon, from 12pm to 6pm. Read More... Once again, DVCon Europe is October 19 and 20 in the Munich City Center Holiday Inn. Get the full details , including a link for registration (sorry, you missed the $50 early registration discount). Oh, and DVCon San Jose is February 27 to March 2, 2017, in the Doubletree as usual. Previous: Cadence Implementation Flow For an ARM Cortex-A73 at 10nm![]()
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