In a previous blog we talked about the IC Packaging Design Variant tool. As you recall, this tool extended and eased the practice of a designer creating one database that represented multiple configurations of the same general design. Rather than manipulating the design for each version (removing wires and die multiple times), this feature allowed the user to keep one database with all the possible members of the design, and then to specify and auto-generate sub-designs with subsets of the die in various configurations. This is a common practice in stacked-memory designs, where the same design might have 4, 8 or 16 die with the same substrate. What if I told you that not only can you now vary the design by its die and wire configurations, but also vary (bias) the geometries that make up the substrate of the design? We have updated the Design Variant functionality in 17.2 to do just that -- to take one design and generate sub-designs that represent the process variation in the manufacturing of the package. This capability allows the user to specify the range in which pads, clines and shapes can vary from the expected size: 17.2 users will notice there is a new section in the Variant tool which allows the user to specify the min/max range (percent or absolute) for each of the items on each layer of the design. The user can then generate new databases with objects modified based on these offsets. Process variations can have significant impact on both DRC and signal integrity. Whereas it is not unusual to be able to bias the artwork generated from a database, this capability allows the user to generate new versions of the database at the minimum, nominal and maximum sizes specified by the user. The same constraints, DRC’s, and signal integrity tools can be run on the resultant databases as were run on the original design --- e.g. if I design a cline to be 5um wide, but my process capability generates clines 5um +/- 5%, how does this variation affect my characteristic impedance? What about my DRCs? What areas of the design are sensitive to process variation, from a yield or SI perspective? This capability can be found under the Manufacturing --> Design Variants feature in SIP Layout XL. Cline (-5%) Nominal (Cline 5um Wide) Cline (+5%)![]()
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