To maximize yield and achieve optimum quality of your final, manufactured IC package substrate, we all want to balance the metal coverage across different layer - and region - pairings of your package layout. But, just how do you go about doing that with your package design tool? With the 16.6 release of Cadence Allegro Package Designer and SiP Layout tools, you can be well on your way to achieving fantastic results in just five minutes and three steps. If this sounds too good to be true, keep reading...(read more)![]()
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