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Balance Metal Coverage Across Different Layers with Ease Using Cadence 16.6...
To maximize yield and achieve optimum quality of your final, manufactured IC package substrate, we all want to balance the metal coverage across different layer - and region - pairings of your package...
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CDNLive 2014: Follow the Data to Optimize System Design--Chris Rowen
SANTA CLARA, Calif.--To understand the past, present, and future of electronics system design, follow the data. That was the message from Cadence Fellow and Tensilica founder Chris Rowen during a...
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Q&A with Nimish Modi: Going Beyond Traditional EDA
Over the past few years, Cadence has evolved from being a traditional EDA tool provider to become a system development partner that is enabling the design of the end products that impact our daily...
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Cadence Sigrity Full-Wave 3D Field Solver Technology Highlighted at CDNLive...
The Cadence user group event in Silicon Valley, CDNLive SV 2014, had a number of different focused topic tracks at the event. For the complete two day agenda, click here . Track 6, the IC Packaging/SI,...
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Stan Krolikoski Video: New IEEE Working Groups Pursue EDA Standards
The IEEE has always been regarded as the final word when it comes to standards that impact electronics design. It is thus significant that several new EDA-related IEEE working groups have recently been...
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Mobile World Congress: Augmented Reality Gets Mobile
BARCELONA, SPAIN—The idea emerged during a game. That's how Markus Meixner describes the inspiration for his augmented reality technology and his company, ViewAR. He was playing a "small game" genre...
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Whiteboard Wednesdays - Understand USB Controllers and Their Performance Specs
In this week's Whiteboard Wednesdays, Jacek Duda provides an informative overview of USB controllers and the potential performance that can be achieved. He also discusses in detail specs for USB 2.0...
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For System Design Complexity, a New Type of Engineer?
Some describe it as a tension. Others described it as a cultural gap or a cultural unfamiliarity. Some suggested, somewhat tongue-in-cheek, completely new naming conventions.But any you slice it, there...
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CDNLive 2014 Paper: HP Engineers Road-Test Cadence Incisive vManager Solution
If you really want to know how a new EDA product works, listen to someone who has thoroughly tested and used it. Verification engineers and managers got a chance to do just that at CDNLive Silicon...
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Mismatch Contribution Analysis in Virtuoso Analog Design Environment GXL
When Monte Carlo analysis shows device mismatch variation has become problematic, Virtuoso Analog Design Environment (ADE) GXL Mismatch Contribution Analysis can provide useful diagnostics as a next...
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Videos, DVCon 2014 Papers – Formal Verification “Apps” Move to SoC Level
Formal verification is a well-accepted technology for block-level verification, and it's now moving up to the system-on-chip (SoC) level. That's the message behind two paper sessions and two poster...
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EDA Verification, IP Innovation Drive System Design: Taneja
SAN JOSE, Calif.-- The old model of innovation "just doesn't work" anymore, and EDA vendors are stepping up their own innovation to keep systems designers more efficient and productive.That was the...
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Whiteboard Wednesdays - Comparing 3D Memory Solutions and Their Market...
In this week's Whiteboard Wednesdays, Scott Jacobson completes his three-part series on the Memory Wall with a discussion on the different 3D memory solutions today and their market applications. You...
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OrbitIO/SIP-XL Co-Design Flow Highlighted at CDNLive SV 2014
The Cadence user group event in Silicon Valley, CDNLive SV 2014, had a number of different focused topic tracks at the event. (See the complete two-day agenda .) Track 6, IC Packaging/SI, PI, featured...
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Applying Software-Driven Development Techniques to Testbench Development
Over the past couple of years there has been some interest in applying a software development technique called unit testing in the hardware development flow. One of the reasons is that unit tests allow...
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IEEE Panel Charts “Top SoC Design Challenges”
What are the top ten challenges in system-on-chip (SoC) design today? Can virtual platforms, cloud computing, and fully depleted silicon-on-insulator (FD-SOI) be part of the solution? Experts discussed...
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System-Design Challenges Abound but So Do Solutions: Panel
SAN JOSE, Calif.—A rising storm of complexity-involving software, electronics, and mechanical components of system design has not stopped engineers from tackling challenges and increasing design...
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“Extreme” Scale EDA Workshop Discusses Research and Funding Priorities
Seeking to empower the future of EDA, around 30 EDA researchers from academia and industry met at the CCC/SIGDA Workshop on Extreme Scale Design Automation in Tampa, Florida in late February 2014....
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Sharing is Learning - New RAKs and Videos for Digital Users on Cadence Support
Friends, you would probably agree that sharing knowledge is a practical way to solve business problems, and contributes to business goals. Thought I'd share some great content that I came across while...
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Incisive Simulation and Verification: Top 10 New Things I Learned While...
In my first blog of this quarterly series, I focused on how Rapid Adoption Kits (RAKs), developed by Cadence engineers, are enabling our users to be productive and proficient with Cadence products and...
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