In July 2012 Cadence announced its acquisition of Sigrity , a leading provider of signal integrity (SI) and power integrity (PI) analysis tools. Jiayuan Fang, Sigrity founder, led the team for the first two years, and has moved on to seek other endeavors. Before doing so, he handed the reins to Dr. An-Yu Kuo. In this interview, Dr. Kuo (pictured below) discusses how Sigrity and its products have become an integral part of Cadence and how things will progress under his leadership. Q: An-Yu, let's start with some background. What is your history with Sigrity and now Cadence? A : Well, since my school days in Taiwan and then my Ph.D work at Illinois, it’s been a great adventure. I founded Optimal Corp. in 1995 to develop simulation software for package designs. Optimal was acquired by Apache Design in 2007. At Apache, I was Chief Architect and worked on integrating IC and package/board thermal simulation tools into a single tool. In 2009, I joined Sigrity as a director to develop a 3D full-wave EM tool, 3DFEM, as well as an electrical/thermal co-simulation function inside PowerDC. I came over to Cadence when it acquired Sigrity two years ago. Q: How do you see Sigrity within Cadence? A : The Sigrity team is focused on advancing analysis products for PCB and IC packaging while integrating with flows that extend into implementation tools as well as analysis flows that extend into the chip. Since the acquisition I’ve been leading the team with a focus on growing the SI and PI business and integrating Sigrity technology within Cadence flows. Q: You were elevated this summer to Engineering Group Director. What are your top priorities right now? A : As you know, the complexity of system design today is unparalleled and engineering teams are under extraordinary pressure to not only manage that complexity but deliver winning products into the market in a timely manner. This spans the entire chip, board, package spectrum. The interdependencies of each affect the other in ways we couldn’t imagine just a few years ago. So, with an eye toward managing the complexity, I’m solidifying the integration of Sigrity technologies with Cadence PCB and IC packaging tools and linking Sigrity technologies with related Cadence tools, such as Virtuoso and Voltus. The opportunity for us to leverage a broad array of tools and solutions within Cadence is huge. I want to make sure our customers have everything at their disposal to succeed. Engineers don’t design in silos today. They think about the system design from Day 1. Our mission is to enable that system design approach, and we want to integrate Sigrity wherever we can in the flow to bring predictable and efficient designs to market. Q: Sigrity technology has been in the Cadence fold now for two years. What synergies does the team get from being in a larger company in terms of development and customer engagement? A : Cadence definitely provides much broader business opportunities to Sigrity technology than before the acquisition. As a result, the Sigrity R&D team has been busy exploring the new opportunities and supporting new customers, both internally and externally. Initially the Sigrity technology has been laser focused on providing an integrated signal and power integrity signoff solution to the Allegro constraint-driven flow for PCBs and IC packages. More recently, we have been able to dedicate some resources to supplementing Cadence’s chip-level power signoff solution, Voltus. Together Voltus and Sigrity can provide a complete chip-package-board power delivery network (PDN) solution. And finally, we have the good fortune of having a design IP team in-house pushing the envelope on memory interface and SerDes PHY technology. Sigrity technology is used in-house to ensure that reference designs work as expected and virtual reference designs that plug and play with Sigrity technology are made available to design IP customers. And this is just the beginning as there is more synergy to be derived from working with other Cadence teams. Q: There are a number of products in the Sigrity product line. Which do you see as the primary products? A : The main products include PowerSI and PowerDC , for power integrity analysis, and SystemSI , for power-aware signal integrity of chip-package-board. Key to any SI analysis is accurate extraction from each fabric, which is accomplished with XcitePI, XtractIM, 3D-EM, and PowerSI. Q: It’s hard to underestimate the challenges surrounding power in complex SoC and system design today. Can you offer some examples of the challenges you and your team are seeing out there? A: The challenges are associated with multi-fabric and multi-physics natures of the problem. For today’s electronics designs, power integrity problems need to be solved with seamless collaboration between chip and package tools. At the same time, power integrity is no longer a pure electrical problem. Electro-thermal co-design and co-simulation has become essential to meet today’s power design challenges. Q: Are these challenges confined to particular applications areas right now, such as consumer or automotive? Or do they run the gamut? A : The challenges today are often connected with high-end consumer and automotive designs, but they also apply to other applications. It really does not matter if your product is targeted for a rack in a data center or a wearable device, managing temperature and power consumption is going to be a priority. Sigrity technology was first to provide an electro-thermal co-design and co-simulation solution and we have seen customers in many different types of industries take advantage of this technology. This includes medical, data center infrastructure, and even mil-aero. Cadence’s unique position to address problems at the chip, package, and PCB level is key to our goals and strategy around system design enablement. Q: Sigrity products have been thought of as expert-level tools. Is that still the case? A: Accuracy is key. We will always strive to provide signoff-level accuracy, which will, of course, require a certain amount of electromagnetic understanding and tool expertise. However, it is also our goal to bridge the gap between non-expert and expert. Much of our technology is focused on providing guidance to the non-expert so that when the design is handed over to the expert, all the first-order issues are resolved. And then, with integration with implementation tools, the expert can efficiently modify a design to resolve the more difficult problems that are uncovered with signoff-level analysis. Q: What's the secret to Sigrity's future success? A: Great technology starts with great people. The keys to our success include a strong R&D team, strong relationships within Cadence – integration with Allegro, Virtuoso, Voltus, and more. I alluded to this earlier, but Cadence is unique among EDA vendors to have chip, package, and PCB design and analysis tools. Sigrity will play an integral role in enabling efficient system design enablement in the emerging markets such as Internet of Things (IoT). Q: You keynoted EPEPS in Portland last week. Can you give readers a snapshot of what you presented? A : My title was “Trends and Challenges of SI/PI/EMI Tools.” I described three major trends I’m observing: the “complete solution,” “parallel computing,” and “consolidated vendors." Complete solutions is the push to give engineers the solutions that allow them to address challenges such as leakage, power, and temperature in multifabric designs. Parallel computing is clearly key to delivering to the customer better performance to speed design-completion time. And vendor consolidation is an important component of the complete solutions theme I discussed. I then covered a few challenges. I touched on Capacity and speed—compute power is increasing and the price falling, but how do we balance accuracy and performance? New technology nodes (3D-IC, FinFET, TSV, and so on) System-level simulation of high-speed lines (from IP to chip to package to board) Q: You’ve been in the industry long enough to have an excellent historical perspective. Issues have gotten much thornier over time as we move deeper into advanced nodes and more sophisticated system design (for example, power). Looking ahead, what are some issues the electronics industry is going to have to pay much more attention in, say, 4-5 years? A : I would name co-design and co-simulation as a key issue for electronics companies and EDA companies to pay more attention. For example, traditionally IP, chip, package, board, and system designers are separated in different groups or companies, using different tools that are isolated with other domains. Many electronics companies now have designated teams/engineers to handle co-design and co-simulation. Q: Let’s step up a level of abstraction for our last question, if you don’t mind: What do you see as the biggest challenge facing electronics system design engineering teams right now? A : Today design challenges, such as jitter control of high-speed lines and EMI of automobile modules, are multi-fabric and multi-physics. It is impossible for a single design group or design engineer to have skills and knowledge covering the wide spectrum, e.g., IP-chip-package-board-system and electrical-thermal-stress. It is up to each company to restructure design teams to foster collaborations among different design teams and even different design companies. With advances in hardware infrastructure (server farms, cloud computing, cheaper and more power,…), it is up to EDA companies to find ways to grab this opportunity with “system-aware” design tools and simulation tools. Brian Fuller Related stories : -- DAC 2014 Panel: Chip, Package, and Board Design Must be Reconsidered -- (Video) Ericsson Meets DDR and PCIe Specs While Avoiding Crosstalk -- (Video) Nexus Interposers and Cadence Tools Enhance DDRx Designs![]()
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