There has been a flurry of activity on COS over that past couple of months. I can't even come close to listing everything, but here are some of the highlights. Be sure to check out the "Training Bytes" section at the end of this post for information on a recent initiative in which Cadence training experts are publishing short video excerpts from our most popular classes. Product Pages 0. Many of the product pages on COS have been enhanced to be more comprehensive so they can act as "hubs" for finding information on a particular product area. Just select "Product Pages->Select a Product" from the main COS landing page, then choose from the list of products and click on "View Product Details" to go to that page. Choose " Virtuoso Analog Design Environment " to access ADE L/XL/GXL information for IC6.X. Here you can get quick links to the ADE XL and ViVA Video Channels, relevant product documentation, the latest postings on the Custom IC Design Community Forum, and more. Application Notes 1. Using Spectre to Simulate IBIS Models IBIS is a fast and accurate behavioral method for modeling input and output buffers. This app note explains and demonstrates how to simulate IBIS models in Spectre circuit simulator. 2. Layout enhancements in IC6.1.6 ISR7 and ICADV12.1 ISR9 Describes new features for layout creation and editing, object selection, via generation, cloning, and more. 3. Implementing Open Access Pin Connectivity Model in SKILL Pcells Describes how to create parameterized cells with pins defined as strong connect, weak connect, and must connect (and explains the differences). 4. Virtuoso Pin Connectivity Model Describes the design objects and APIs used to define connectivity in Virtuoso Schematic Editor and Virtuoso Layout Editor. It explains how to create and access these objects through both SKILL and the GUI. 5. Demystifying NCELAB This is an update on one of the most frequently downloaded documents on COS. It explains the errors that are most frequently encountered at the elaboration phase of running AMS Designer. Each error description includes an example testcase and the steps needed to resolve the error. 6. Spectre PSPICE Netlist Support Walks through the new feature in MMSIM 14.1 that enables the user to include PCB components in PSPICE format into a Spectre simulation. Rapid Adoption Kits (RAKs) 7. ADE Verification Workshop The workshop demonstrates how to characterize an ADC using Spectre and the Virtuoso Analog Design Environment. What you will learn: Evaluate ADC Effective Number of Bits, Dynamic Comparator Characterization, Capacitor D/A Converter Characterization, Clock Generator Characterization. 8. IC 6.1.6 Pin-to-Trunk Device-Level Routing (Updated for IC 6.1.6 ISR8) This material steps through the Pin-to-Trunk Device-Level Routing Flow in Virtuoso in IC 6.1.6. The objective of this flow is to increase layout productivity through improved routing functionality aimed at device-level interconnect. This flow enables users to quickly connect device pins in a structured topology. What you will learn: Pin-to-Trunk Routing Basics, Pin-to-Trunk Routing with Wire Assistant Overrides, Pin-to-Trunk Routing with Routing Scope and Via Control. 9. IC 6.1.6 Pin-to-Trunk Block_Level Routing (Updated for IC 6.1.6 ISR8) This material steps through the Pin-to-Trunk Block-Level Routing Flow in Virtuoso in IC 6.1.6. The objective of this flow is to increase layout productivity through improved routing functionality aimed at block-level interconnect. This flow enables users to quickly connect block pins in a structured topology. What you will learn: Pin-to-Trunk Routing Basics, Using Pin-to-Trunk Routing to Route Between Blocks. 10. Liberate AMS For Characterizing Mixed-Signal Blocks (Command-line Flow) Static Timing Analysis (STA) on modern SoC designs includes paths that go through digital blocks embedded in AMS blocks. There is a need to generate accurate liberty (.lib) files for these AMS blocks that contain analog block pins that interface with digital blocks. Tools used for generating liberty files for standard cells, I/O, or memories cannot handle such blocks due to their large size, difficulties in handling the included analog circuitry, time required to run accurate simulations, etc. Liberate AMS is architected to characterize large macro blocks containing complex custom digital and analog components like PLLs, SerDes, data converters, etc., for timing, power, and noise. What you will learn: Intro to Characterization of AMS IP Blocks, Characterization Terminology, Essential Liberty Syntax; Tool Overview, Setup for Characterization, Output Files, Debug, Troubleshooting. 11. Split Connect Rules This example describes how you can use the Split Connect Modules (CM) in your design in the command line flow. By default, Merged Connect Modules (CM) are inserted in your design. So, you have to create either user-defined connect rules or different ie cards in order to use the Split Connect Modules. What you will learn: Creating split connect rule in amsd block, Running Simulation and Checking Results, Checking connect rules/modules in the log file. 12. SDF Annotation flow for AMS Simulations from Virtuoso ADE This material provides an overview about how to use the SDF file in the AMS simulation flow. The document provides the knowledge needed to annotate timing data to your Verilog designs and to understand the Standard Delay Format (SDF) for simulation and annotation purpose. It also explains some of the SDF keywords, discusses some issues you may encounter and demonstrates the annotation process. What you will learn: General Introduction to SDF, Verilog SDF Annotation, Test case, Most frequent Errors and Warnings. 13. Voltus-Fi EMIR Analysis Workshop This workshop covers the basics of Voltus-Fi-based transistor-level electromigration and IR-drop analysis. The flow is integrated with APS/XPS simulators that use a new technology designed to provide very high capacity and performance. What you will learn: Running QRC to generate a good DSPF for EMIR analysis, setting up EMIR analysis options in ADE-L and XL, followed by analysis of results in Virtuoso Layout Editor. You will also learn about the key layout debugging capabilities of the Voltus-Fi solution. 14. Static and Dynamic Checks This material describes the usage of the Spectre APS/XPS static and dynamic design checks available in MMSIM13.1.1. These checks may be used to identify typical design problems including high impedance nodes, DC leakage paths, extreme rise and fall times, excessive device currents, setup and hold timing errors, voltage domain issues, and connectivity problems. While the static checks are basic topology checks, the dynamic checks are performed during a Spectre APS/XPS transient simulation. What you will learn: Use model, Static check, Dynamic check Solutions 15. Role of portOrder and CDF termOrder in Verilog and auCdl Netlisters When we netlist a schematic, the ports or pins of a subckt or module are listed in a particular order. Different netlisters decide this order of pins in different ways. In this document, we are going to cover how OSS-based netlisters like auCdl and Verilog handle this pin order via CDF termOrder and portOrder property. 16. How to get an email sent to user after ADE XL simulation is completed Contains an example of how you can connect a procedure with the runFinished trigger to send an email on completion of an ADE XL run. 17. How to run simulations diagnostics for a given time window or range? New options in MMSIM 14.1 to limit the printing of simulation diagnostic information within a specified time range. Videos 18. AMS Unified Netlist (UNL) Quick Start Quick start video showing setup and usage of the new AMS UNL flow in the Virtuoso solution. All existing and new users to AMS ADE are strongly recommended to migrate to AMS UNL flow. This video is meant to aid in the immediate proliferation of the non-default, production status of AMS UNL. To use, setenv AMS_UNL=YES. 19. Compelling Advantages in Migrating your AMS OSS Netlisting Flow to the New AMS Unified Netlisting (AMS UNL) Flow Present the seven main advantages in migrating your AMS OSSN flow to the new AMS UNL flow: 1) Retain use of SpectreCDF siminfo, 2) Enhanced irun binding engine, 3) Enhanced black-box design unit methodology, 4) Full VHDL/VHDL-AMS support, 5) Enhanced schematic/text bus handling, 6) Shadow-free text netlisting flow, 7) Symbol-free text netlisting flow. 20. Compelling Advantages in Migrating your AMS Cell-Based Netlisting Flow to the New AMS Unified Netlisting (AMS UNL) Flow Present the three compelling advantages of migrating your AMS Cell-Based Netlisting Flow to the new AMS Unified Netlisting(AMS UNL) flow: 1) Use existing SpectreCDF siminfo without having to create and maintain ams siminfo, 2) Use irun single-step executable, 3) Ability to reference text cellviews external to Virtuoso by using the black-box design unit(BDU) methodology 21. Creating Pad/Core/Block Rings Using Power Router A set of three videos demonstrating how to create pad, core, and block rings using the power routing GUI in the Virtuoso solution. Also shows SKILL commands that can be used instead of the GUI approach. 22. Back Annotation of Modgen Dummies This video demonstrates how to create a Modgen constraint, add dummies, and back annotate the dummies to the schematic. 23. Bindkey and Access Keys - Features to Improve Productivity - An Overview It shows the pane showing tools for which bindkey is defined. Format of a bindkey. How to add a bindkey. Duplicate bindkey warning. Access keys. 24. Distributed Processing in ADE L It demonstrates "How to use Distributed processing from ADE L with LSF". It has been made on IC616ISR8. Training Bytes 25->Very Large Number. Did you see the latest video segments in the Video Library? Cadence course developers are now creating and sharing Training Bytes from their course materials. These short videos help you learn a task or topic in a few minutes. Go check them out in Video Library and send feedback via the Feedback box. There are way too many to list here individually, but this is a little taste (ha-ha, "bytes"—"taste", get it?). I'm running out of time to add all the individual links, but you can find them all with a quick search or just select Resources->Video Library to see the full list. From the course: Virtuoso Layout Pro Create Via Command Alignment Commands Using the Wire Editing Options with Create Wire From the course: Virtuoso Layout for Advanced Nodes Double Patterning—Top-Level Shapes and Instances FinFET Folding Creating and Editing Guardrings in Advanced Node Technology From the course: Virtuoso Layout Design Basics Brief Overview of Dynamic Display Overview and Demo on Creating Instances as Mosaics Overview of Selection Options Form From the course: Virtuoso Analog Simulation Techniques Performing Corner Analysis in ADE XL Operating Region Checks in ADE XL Variables and Parameters in ADE XL![]()
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