System developers want semiconductor IP models that are fast, accurate, flexible, adaptable, and easy to verify and integrate. Both internal and external providers of IP are working to fulfill these requirements, but more needs to be done, according to panelists at the DesignCon 2015 conference on January 28. The panel session, titled System-Level Modeling for IP Enablement , was convened to consider modeling requirements for IP in a systems environment. The focus was not on standalone IP, but on the PHY and the entire system within which the IP will be applied. Panelists represented IP developers, IP users, system designers, and EDA providers. Panelists were as follows, shown left to right in the photo below: Brad Brim (moderator), senior staff product engineer for high-speed analysis products, Cadence Chao Xu , senior director of communication system hardware, Inphi Kevin Roselle , senior staff engineer, Qualcomm John Lupienski, product engineer director, Design IP Group, Cadence Taranjit Kukal, product engineering architect, Cadence “We normally think of IP modeling as enabling systems,” Brim said as he introduced the panel. “But it a sense it’s the reverse—system level modeling can actually enable IP.” Brim came to Cadence from Sigrity , a provider of package and PCB signal integrity and power integrity tools that was purchased by Cadence in 2012. He noted that what was previously an “outsourcing” flow became a “one-team effort” as Cadence entered the IP market, enabling shorter IP design and verification cycles, greater system application breadth, and more robust IP. The IBIS-AMI standard was frequently mentioned during the panel discussion. The traditional IBIS standard, which stands for Input/Output Buffer Information Specification , is a standard data exchange format for semiconductor device suppliers, simulation software providers, and end users. IBIS-AMI ( Algorithmic Modeling Interface ) is a modeling standard that allows fast simulations for SerDes PHYs. Chao Xu—A User Perspective Xu is a system designer at Inphi , a provider of high-speed analog/mixed-signal semiconductors. He noted that multiple types of IP models are needed for system design, including: Fast behavioral-level models that can be used for “what if” analyses IBIS-AMI models that are also fast, but related to the real circuit Encrypted circuit-level models for high accuracy “Finally, when the IP design is finished and circuit designers put everything together, we want silicon-level models. But this is not always provided by IP vendors, especially at 32 Gbits/second and above,” Xu said. He also noted that IP models must be correlated with measurements in the time domain, frequency domain, and statistical domain. At the system level, IP should include an on-die diagnostics feature, Xu said. This makes it possible to see what is happening inside the chip, providing “in situ” system-level debugging. Xu also observed that IP “needs to include flexible and adaptive DSP features” that let designers make power and performance tradeoffs. Kevin Roselle—Both a User and a Provider Roselle brought a unique perspective to the DesignCon panel. “I supply IP models to customers and I’m a consumer of IP models, so I get it from both sides,” he said. Roselle set forth some tough requirements for IP models. First on his list is “highest accuracy possible.” With DDR IP, Qualcomm designers usually get encrypted transistor models, which they view as highly accurate. But it’s rare to get a transistor model for SerDes these days. “15 years ago we got those, but now we get AMI models of some sort,” Roselle said. A second requirement is the ability to factor in all parameters and controls, whether it’s drive strength, or slew rate, or something else. “It would be good if I could do all those tweaks concurrently and not have to look at 30 different models,” Roselle said. A third requirement is to model the power integrity effects of all the rails in the IP. It is “hard but not impossible” to use IBIS models for that, and sometimes Roselle has to go back to the transistor level to look at jitter insertion and power supply noise. Finally, Roselle said, IP models need to be at least 10X more efficient than transistor models in terms of execution speed and memory requirements. He has seen transistor-level simulations that take up a whole blade server and run for a week. With SerDes, Roselle said, Qualcomm has confidence in the AMI bit error rate (BER) results—at least in terms of correlation with lab data. “We still don’t know about correlation with the real silicon device,” he said. “We also don’t know how well the AMI models are characterized over process, voltage, and temperature. I suspect a lot are not.” Roselle pointed out that it takes a lot of effort to model jitter using IBIS-AMI. Roselle observed that “behavioral models are always trailing the semiconductor industry.” When SerDes came out in the late 1990s, for instance, designers ended up using transistor models and grinding through long simulations. What’s coming out now are parallel buses at SerDes speeds, and advanced models are still needed, Roselle said. Also needed is closer linkage between IP developers and EDA developers, so advanced simulation capabilities roll out before or concurrently with new IP capabilities. Taranjit Kukal—Improving Quality Kukal said that behavioral modeling has improved design quality at Cadence. “The model becomes a way to qualify if the design is correct,” he said. For example, IBIS-AMI modeling and PHY correlation makes it possible to estimate how much of the design is away from ideal behavior, and helps designers figure out areas of improvement. But there are tough challenges from an IP provider viewpoint, and test is one of them. “How many packages, how many PCBs, how many combinations will you try?” Kukal asked. “You have to pick testbenches for all those combinations.” John Lupienski—Challenges for Developers Lupienski was an IP developer and user in the past, and today he works with Cadence IP customers both before and after sales. He is thus very familiar with the challenges facing IP developers. One challenge is that PHY IP product development time is increasing with advanced process nodes. As PHY development becomes increasingly difficult, providers want to cover as many data rates and protocol standards as possible with one PHY. Lupienski also noted that Cadence spends a lot of time in silicon qualification. “You can show people PowerPoint, but you somehow have to give customers a vehicle to road-test the IP,” he said. “You can give the customer a fully qualified model across all corners, but if you have a typical list of standards and rates, it’s a significant undertaking.” The panel concluded with a question-and-answer session that explored such topics as model accuracy, non-linearity, the evolving IBIS standard, low-power design, and high-speed design. In all, it was a spirited discussion with perspectives you don’t often hear when it comes to IP development, modeling, and integration. Richard Goering Related Blog Posts - Why Cadence Bought Sigrity—and How it May Change PCB Analysis - Cadence Firmware Packages Enable Successful IP Integration - DesignCon 2015—What Happens When Chips Meet Boards![]()
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