Small is Beautiful—How UVM Test Case Extraction Can Improve Your Constraint...
In the world formerly known as microelectronics, which is now actually nanoelectronics, small is sure beautiful. With the continued reduction in transistor size, we can afford to pack an insane amount...
View ArticleDesignCon 2015: How a Problem-Plagued Networking Project Gave Birth to...
SANTA CLARA, Calif.—Turns out the mother’s milk of innovation is, well, MILC. Money, ignorance, luck, and craziness are the four essential ingredients to success, according to Stanford Engineering...
View ArticlePablo Picasso and the Power of Abstraction: Make Sense of Your Verification...
Abstraction is a key concept that makes it easier for humans to deal with large and complex systems. Since abstraction reduces complexity, without abstraction, hardly any innovation would be possible...
View ArticleDesignCon 2015: Tackling PCB Design Issues with New Sigrity Technology (video)
SANTA CLARA, Calif.—For Brad Griffin, DesignCon is like Christmas in January. New tool and scope technologies are everywhere, and the engineering audience that strolls the exhibits is among the most...
View ArticleLow-Power Summit: Optimizing for Power in Advanced Wireless Systems
In big wireless networks, little things matter big time when it comes to power. That was the message from Elad Alon , a UC Berkeley professor ( pictured left ) involved in research at the university’s...
View ArticleBefore There Was a Transaction, There Were Signals
Transaction-based verification has been around for many years. A transaction is an abstraction that consists of a single transfer of data and control signals. With today’s complex SoCs, we need to...
View ArticleDesignCon 2015 Panel: Why System-Level IP Modeling Is Difficult
System developers want semiconductor IP models that are fast, accurate, flexible, adaptable, and easy to verify and integrate. Both internal and external providers of IP are working to fulfill these...
View ArticleHiSilicon collaborates with Cadence on DDR4 PHY IP for TSMC 16FF
High-performance and high-speed memory design characterized by low-power operation are requirements for today’s leading edge electronics. Cadence is a leader in providing advanced process node,...
View ArticleDesignCon 2015 Panel: The Biggest Challenges with System-Level Power Modeling
SANTA CLARA, Calif.—Modeling power properly can make or break a product’s success, but with today’s electronic systems, that’s easier said than done. There appears to be no system-level modeling “Holy...
View ArticleWhat's Good About Allegro PCB Editor Thieving? 16.6 Has Several New...
The following enhancements have been made to the 16.6 Allegro PCB Editor Thieving application. Thieving outline: New ‘Rectangle’ option added to the list. If selected, the user is required to make only...
View ArticleWhiteboard Wednesdays—ARM AMBA Microcontroller Protocol Family
In this week's Whiteboard Wednesdays video, the first of a two-part series, Avi Behar explains the ARM® AMBA® (Advanced Microcontroller Bus Architecture) protocol family. Many of the protocols, from...
View ArticleWhat's Good About Using Sigrity to Gain Signal Access? Check Out This Expert...
This week, you can view a video where a customer describes how they used the Cadence® Sigrity™ PowerSI® tool to enable their team to run what-if cases to gain insights that lead to useful changes in...
View ArticleVirtuosity: 26 Things I Learned in November and December 2014 by Browsing...
Happy New Year to all from the award-winning Virtuosity blog team (Alice, Praveena, Rajesh and myself)! Okay, so it was an internal Cadence Standing Ovation Team Award, but it works for me. There are...
View ArticleWhat's Good About Using Allegro TimingVision and IPC-2581 to Reduce Design...
This week, you can view a couple of videos where customers describe how they used Cadence's Allegro TimingVision technology to achieve 4X faster timing closure on DDR3 and DDR4 memory subsystems of...
View ArticleWhat the ARM Cortex-A72 Processor Announcement Means for Electronic System...
ARM this week announced a new premium mobile IP suite that includes ARM’s Cortex-A72 64-bit processor core, ARM Mali-T860 and T880 GPUs, and a new, faster ARM CoreLink tool. In tandem, Cadence...
View ArticleBlast From the Past—Or Debugging HDL Race Conditions And Glitches
In 1999, the movie Blast from the Past was released. It begins in Los Angeles in the 1960s, during the Cold War era. In this movie, a nerdy, engineering-type father was afraid of a potential conflict...
View ArticleWebinar: Smart Sensor Design Links MEMS to IoT
Micro-electro-mechanical systems (MEMS) sensors will play crucial roles in many Internet of Things (IoT) devices. In a newly archived webinar, experts from ARM, Cadence, and Coventor show how to design...
View ArticleHeading Off the Butterfly Effect—The SimVision "Quick Diff"
Functional Verification Debug Blog - SimVision Gems Most engineers are familiar with the “ Butterfly effect ” – the notion that a small change can result in enormous repercussions in the future. A...
View ArticleDesignCon 2015: Why Complex PCBs Require New Types of Layout Checks
Are you running design rule checking (DRC) on your PCB layouts? You should—but DRC alone is not sufficient for complex, signal-integrity prone boards, according to a recent presentation by Joy Li...
View ArticleWhere’s My Star Trek Lifestyle?
The sparkle seems to have gone out of the Internet of Things (IoT) market for the moment, and this is a problem because it means my Star Trek lifestyle is now on hold. The ambitious Google Glass...
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