HiSilicon collaborates with Cadence on DDR4 PHY IP for TSMC 16FF

High-performance and high-speed memory design characterized by low-power operation are requirements for today’s leading edge electronics. Cadence is a leader in providing advanced process node, low-power memory IP. Recent news with Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) and HiSilicon Technologies Co. Ltd highlights our collaboration to meet the needs of industry leaders in this area. This is the first customer to license the Cadence ® Denali ® DDR4 PHY IP, implemented on the TSMC 16nm FinFET process. HiSilicon, TSMC, ARM, and Cadence As a leading provider of chip solutions for communication networks and digital media, HiSilicon used TSMC’s advanced FinFET technology to produce the industry’s first networking processor with processing speeds up to 2.6GHz. The processor is based on the ARMv8 architecture, as a result of HiSilicon’s relationship with ARM . Cadence was also a key part of the project. HiSilicon “broadly adopted Cadence digital and custom/analog verification solutions, and has licensed Cadence DDR IP and the Cadence 3D-IC solution to deploy multiple heterogeneous dies in a single package on a silicon interposer substrate”, as announced in a December press release . Technology What is interesting about this project is HiSilicon took advantage of 16FF to realize the full performance of the DDR4 standard. TSMC 16nm FinFET entered risk production in November 2013. It enabled “a significant leap in performance and power optimization” for HiSilicon’s networking processor, according to TSMC. DDR4 memory technology, with maximum speeds of 3.2Gbps pin rate, is ramping up with its adoption in datacenters . As cost comes down, client devices are expected to be the next growth segment. These applications require a complete solution. The Cadence DDR4 PHY IP is fully compatible with the Cadence DDR4 Controller IP, offering these key benefits: A major design objective is maximizing low-power consumption with high-speed. The design incorporates 32-bit DDR 4 PHY with de-skew architecture that supports per bit DQs and CA. The slice-based architecture ( presented below ) ensures support for a wide memory class and data rate range. The IP is silicon-proven in TSMC testchips, and at customers such as HiSilicon. DDR4 PHY IP with Slice-Based Architecture - System-Level Example Use Cadence offers a broad portfolio of IP for advanced process nodes from TSMC, including PCIe, Analog, MIPI, Ethernet, and many more. For more details regarding the full Cadence portfolio visit our DIP website and for specific features of our DDR4 PHY IP, go to the DDR resource page . Steven Brown Related stories: -- DDR4 Roadmaps and Strategic IP Planning -- DDR4 in 16nm FinFET: Future proof your SoC design