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What's Good About DEHDL’s Constraints Comparison? The Secret's in the 16.6...
The Allegro 16.6 Design Entry HDL release provides designers a mechanism to compare two databases for constraint differences. The databases that can be compared are of the following types: • Schematics...
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Answers to Top 10 Questions on Performing ECOs in EDI System
Applying ECOs to a design can be complex, stressful and error prone so it's important to apply the right tools and flow to implement the changes successfully. EDI System provides multiple ECO flows to...
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What's Good About FSP’s Design Compare? Check Out 16.6!
The 16.6 Allegro FPGA System Planner (FSP) product has an extremely helpful Design Compare capability.With design changes done in Allegro PCB Editor the FSP designer needs to verify and, if they agree,...
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Electronic System Level (ESL) Design Gets a Pragmatic Look at EDPS Workshop
Presentations at the Electronic Design Process Symposium (EDPS) April 18, 2013 gave a realistic look at the promises and limitations of electronic system level (ESL) design. Speakers noted that ESL...
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Develop For Debugability – Part II
Looking at Coding Styles for DebugIn this blog post we are going to discuss 3 different cases where coding style can help you debug easier: 1. Declarative vs. Sequential Coding 2. Method Call...
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SKILL for the Skilled: Many Ways to Sum a List (Part 8): Closures --...
In the past several postings to this blog, we've looked at various ways to sum a given list of numbers. In this posting I'll present yet another way to do this. This time the technique will be markedly...
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Panel: 3D-IC Design Experts Tackle “Practical Issues” in 2.5D and 3D TSV...
3D-IC technology has gone from the "grandiose plans" of several years ago to the "practical issues" of ramping up for widespread deployment, according to one panelist at the Electronic Design Process...
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Cadence DAC 2013 and Denali Party Update
A very special Design Automation Conference (DAC) will take place in early June - it's the 50th anniversary of this conference, which has long been a focal point of the EDA industry. This year Cadence...
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GLOBALFOUNDRIES at CDNLive: Why 10nm Requires Design Technology Co-Optimization
It's not too early to start thinking about the 10nm process node and beyond - but such advanced process nodes will require a significant change in the semiconductor design ecosystem, according to...
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What's Good About ADW’s Design Migration? 16.6 has many new enhancements!
Prior to the Allegro Design Workbench (ADW) 16.6 release, the migration process required multiple executables:– Netassembler – Archiver – Purge– PackagerIt was also less robust with...
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EDPS Workshop – a Review of FinFET Parasitic Extraction Challenges
There's a lot of excitement about the use of FinFETs at advanced process nodes, and no wonder, given their potential power and performance advantages over planar transistors. But CAD and methodology...
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Creating Virtual Platform Models
One of the most common questions asked about virtual platforms is: Who creates the models? There are many sources of models and there are people who can make additional models (like Cadence), but...
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Designer View – How GigaOpt in Encounter Digital Implementation (EDI) System...
If you want to design faster chips in a shorter period of time, the new GigaOpt preRoute technology in the EDI System 13.1 release may be the solution. A detailed look at the GigaOpt preRoute...
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Customer Support Recommended - Instance and Occurrence Modes of Design...
Assigning reference designators for the schematic instances is a very vital part of the entire PCB flow. This can sometimes become very cumbersome, and in some cases users allocate a major portion of...
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Turn GDSII Data into Intelligent Die Components with 16.6 Cadence APD/SiP Tools
As we all know, there are many file formats in which an IC package designer will receive a die from the IC designer. Ideally, it will be in a format such as die text or a co-design die abstract, as...
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Joe Costello at EDAC: “Secrets” for Telling a Compelling Company Story
There is no doubt that Joe Costello, the first Cadence CEO, knows how to tell a compelling company story. Under his charismatic leadership, Cadence experienced explosive growth after its formation in...
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What's Good About Capture’s Save Command? 16.6 Has a Few New Enhancements!
Just a quick blog this week to mention a couple productivity enahancements for Capture-CIS. The 16.6 Allegro Design Entry CIS (Capture) product has a few new enhancements for Saving designs.Read on for...
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New Incisive Low-Power Verification for CPF and IEEE 1801 / UPF
On May 7, 2013 Cadence announced a 30% productivity gain in the June 2013 Incisive Enterprise Simulator 13.1 release. Advanced debug visualization, faster turn-around time, and the extension of eight...
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Mode Support for SimVision “Stop Simulation” Button
Prior to Incisive Enterprise Simulator (IES) 12.1, clicking the SimVision "Stop Simulation" button would stop the simulation both in an HDL context and in a Specman context if Specman was present in...
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Things You Didn't Know About Virtuoso: Delta Markers in ViVA
This article is dedicated to the gentleman I sat next to at lunch at CDNLive a while back who Is a CAD engineer busily supporting a large user community, but had been stumped by the question "How do I...
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