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USB 3.2—The USB Type-C Connector Finally Met its Match
It’s only a week before the first event of USB Developer Days , a series of meetings for USB developers, where the USB 3.2 specification will be formally announced. Much like with any recent smartphone...
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Whiteboard Wednesdays - Implementation Challenges of Embedded Automatic...
In this week’s Whiteboard Wednesdays, Raul Casas, systems architect IP group, talks about the challenges in designing automatic speech recognition (ASR) systems for performance, cost, and power...
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India, Singapore, Hong Kong
What do India, Singapore, and Hong Kong have in common? Well, I visited them all a couple of weeks ago, that's one thing they have in common. They all drive on the left, that's another. There's a...
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CDNLive India 2017: ThinCi on AI, Machine Learning and Deep Learning
Last week’s blog was about Venu Puvvada’s keynote at CDNLive India. Today’s blog is about the second keynote we had (on Day 2 of CDNLive India) by Dinakar Munagala, CEO of ThinCi Inc (pronounced...
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Coincidence and Another Record
Record 1 I recently reached a sort of record that I detailed in my post The 500th Breakfast Bytes Post . Record 2 On my way back from CDNLive Boston, I was in Boston Airport (well, what a surprise)....
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Show Me the Money
I have put out some posts about generic business models and startups. However, if you want some advice that is more EDA-specific, then at DAC a couple of years ago (before I was back at Cadence) Jim...
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Virtuosity: Sweeping Multiple DSPF Views in ADE
Wouldn't it be great if you could have a view for your DSPF files and sweep them in an ADE session without having to add them as simulation files? Well now you can! You can create a DSPF view just like...
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What's For Breakfast? Video Preview September 25th to 29th 2017
(Please visit the site to view this video) Coming from Testarossa Winery, Los Gatos (camera Corrie) Monday: EDPS Tuesday: SEMI Strategic Materials Conference Wednesday: Jim Hogan at SJSU Thursday:...
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The Art of Analog Design: Part 3, Monte Carlo Sampling
In Part 2, we looked at Monte Carlo sampling methods. In Part 3, we will consider what happens once Monte Carlo analysis is complete. Of course, we will need to analyze the results, so let’s look at...
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Making it Easier to Apply Palladium Z1 to SoC Performance Analysis
Recently, Renesas combined the Cadence® Interconnect Workbench, the Cadence vManager™ Metric-Driven Signoff Platform, and the Cadence Palladium® Z1 Enterprise Emulation Platform to improve their...
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EDA Summer Camp—Cadence Taiwan Hosts Top University Students
To help more students majoring in Electronics Engineering increase their understanding of the EDA industry and find their future direction, the EDA group of Graduate Institute of Electronics...
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Follow Video-Embedded Troubleshooting Articles for Easier Debugging
Finding a way out of situations is routine in today’s ever changing world—more so in the world of tech. Our problems range from trivial to critical. Mostly, people look for simple solutions that are...
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When Arm meets Intel – Overcoming the Challenges of Merging Architectures on...
As the stakes for winning server segment market share grow ever higher an increasing number of companies are seeking to grasp the latest Holy Grail of multi-chip coherence. The approach promises to...
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Solving the Design to Manufacturing Problems in Milpitas
HOT NEWS: In case you missed it, right at the end of last week, British GPU and CPU (MIPS) maker Imagination was brought by Canyon Bridge, Chinese money but run out of Palo Alto. One of the partners is...
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Headlines that Caught My Eye Last Week
Part of my job is to keep an eye on what's going on in the tech world, especially how it relates to Cadence technology. These few articles caught my eye, so I wanted to share them with you. Researchers...
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SEMI Strategic Materials Conference
Yesterday I wrote about EDPS, which takes place at SEMI. Today, I'm writing about SEMI's Strategic Materials Conference (SMC), which doesn't take place at SEMI but at the Doubletree. A few decades ago,...
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Single Core vs. Multi Core: Simulation in Stereo
Latency simulations are the sworn enemy of the verification schedule. A handful of tests add days to weeks for each regression cycle; and when you add in the fact that they can’t be parallelized like...
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Whooooo Are You? Who, Who? Who, Who?
I woke up in a Soho doorway A policeman knew my name He said you can go sleep at home tonight If you can get up and walk away Well, who are you? (who are you? who, who, who, who?) I really wanna know…...
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What's For Breakfast? Video Preview October 2nd to 6th 2017
(Please visit the site to view this video) Coming from my car (camera Sean) Monday: AMD's early experiences with PSS Tuesday: Accelerating deep learning with Tensilica Wednesday: Jim Hogan at SJSU...
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New Generation CAS Conference
The NGCAS 2017 conference (New Generation of Circuits and Systems) is the first conference from IEEE CAS Society which is targeted at Young Professionals, i.e. on postdocs, who are still in academia or...
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