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Interview with Lip-Bu Tan, Part 1 – How Cadence is Positioned to Build Upon...
Under the leadership of Lip-Bu Tan, Cadence President and CEO, Cadence has experienced strong growth during the past four years. In addition to steadily growing its revenue and hiring hundreds of new...
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Configurable Specman Messaging Webinar Archive Available Now
Configurable Specman Messaging for Improved ProductivityWebinar Archive Available Now!Hello Specmaniacs:Ever wondered how to switch on all messages, or how to switch all of them off? Or get confused by...
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Create Optimum Pin Assignments for FPGAs on PCBs - Part 1 of 2
In most FPGA-based boards, the PCB designer is on his own -- with little help from any tool -- to unravel what is often a routing nightmare. This can be caused by FPGA and/or schematic designs that...
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SKILL for the Skilled: How to Copy a Hash Table
In this posting I want to look at ways to copy a hash table in SKILL. There are several ways you might naively try to do this, but some of these naive approaches have gotchas which you should be aware...
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Imagining Human-Computer Interfaces in 10 Years
MENLO PARK, Calif.--The first real question about security and privacy emerged more than an hour into an expert panel on the future of human-computing interfaces (HCI). That could be a function of the...
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25th Anniversary: Hogan on EDA History and Three Little Words
In the quarter century that Cadence has existed as a company, one man who was there from day one says it has always been defined by three French words. "Cadence has never lacked for esprit de corps,"...
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How Do You Route Your Highly Constrained PCBs? (Part 1 of 2)
How routing is performed to meet the design intent of designers and engineers seems to be a topic of constant debate. Is manual routing better than automatic routing? Is designer-guided,...
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EDA Inches Closer to Cloud Computing
MOUNTAIN VIEW, Calif. -- If you want a glimpse of the future of cloud computing and EDA, there's probably no better place than in the shadows of Google.In that shadow, literally a stone's throw from...
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Video: Alberto Sangiovanni-Vincentelli on Founding Cadence, and the Next 25...
Alberto Sangiovanni-Vincentelli, professor of Electrical Engineering and Computer Sciences at the University of California at Berkeley, was not only a founder of Cadence - he was a founder of the EDA...
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Programmable Memory BIST– A New Direction for Design for Test (DFT)
Memory built-in self test (MBIST) is a design for test (DFT) methodology that has been around for many years. But until now MBIST algorithms have generally been hardwired -- they can't be changed once...
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HDMI 2.0 – Ushering in the Next Generation of Ultra HD TV
The future of television is being defined by two key technologies: organic light-emitting diode (OLED) screens and ultra high definition (Ultra HD or "4K TV") standards. OLED is a display technology...
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DRAM Price Spikes; Engineering Productivity; Get a Date (Great Reads 9-7-2013)
There's more to the world than global conflict. Here are some things from our world that caught my eye: Sneeze in Wuxi; Catch Cold Globally A fire at SK Hynix's Wuxi, China, fab is going to disrupt the...
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Create Optimum Pin Assignments for FPGAs on PCBs - Part 2 of 2
In part 1 of this blog, I discussed a scenario that PCB designers working with FPGA-based boards are often faced with: getting pin assignments from FPGA and/or schematic engineers that can create...
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Palladium XP II – Two New Use Models for Hardware/Software Verification
As you would expect with a new release of a hardware acceleration and emulation environment, the Cadence Palladium XP II Verification Computing Platform -- announced Sept. 9, 2013 -- is faster and has...
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What's Good About Allegro PCB Editor Shape Contraction and Expansion? Check...
The 16.6 Allegro PCB Editor includes new enhancements to effectively manage shape operations.Read on for more details …Shape Expansion/ContractionThe ability to contract or expand an existing shape(s)...
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Interview with Lip-bu Tan, Part 2: Energizing the Electronics Industry
My colleague, Richard Goering, and I spent time with Cadence CEO Lip-Bu Tan to get his thoughts on the company, on the EDA industry and electronics business, and design trends in general. In part 1 of...
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SKILL for the Skilled: Visiting All Permutations
In this posting I want to look at several ways of generating permutations of a list. The problem comes up occasionally in fault analysis as well as a few other applications.Don't generate the list It...
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Live Q&A: Tackling Memory IP Challenges
If you're a design engineer trying to navigate the world of changing intellectual property (IP) standards and how this affects your electronics system and subsystem designs, you have some choices: Ask...
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Virtuosity: 15 Things I Learned in August by Browsing Cadence Online Support
Our folks over in Physical Design have been busy churning out helpful Rapid Adoption Kits to demystify lots of useful features in the Virtuoso Layout Suite. It's a great opportunity to learn some new...
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Designer View: Why We Used Specman for FPGA Verification
Advanced functional verification techniques like constrained-random test generation are well established for ASICs, but not so much for FPGAs. At a recorded Cadence Theater presentation at the 2013...
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