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DVCon 2014 Panel: Did We Create the Functional Verification Gap?
Could standardized functional verification approaches actually be an impediment to success? In a panel provocatively titled "Did We Create the Verification Gap?" at the DVCon 2014 conference on March...
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Cadence Announces Verification IP for MIPI SoundWire™ and C-PHY
Anyone who has been involved in designing mobile devices in recent years is familiar with the MIPI alliance -- a non-profit organization, which took the mission to standardize all interfaces of mobile...
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Sealing the Seams in System Design
Our Cadence colleague, Nimish Modi, SVP of Marketing and Business Development, has called them "seams": gaps that emerge as electronics system design gets more complex. These seams occur when teams...
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CDNLive 2014: Lip-Bu Tan Cites Opportunities and Challenges for Electronics
While several key drivers are propelling semiconductor industry growth, the technical challenges are acute and the end markets are demanding. And that opens new opportunities for Cadence and its...
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CDNLive: Envisioning the Future of IP-Driven System Design
SANTA CLARA, Calif.—The path to tackling system design complexity runs straight through system-on-chip (SoC) IP design and methodology, because getting differentiated systems to market in a timely...
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Patent Debates; Synthesis Evolves; CDNLive Wrap (Electronics Week in Review...
We ended a wild three-week stretch of electronics-industry events with patent debates at Stanford, packed sessions and visionary keynotes at CDNLive in Santa Clara and, of course, Pi Day.
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DVCon 2014 Video: An Update on the UVM 1.2 Release
Since its initial release as an Accellera standard three years ago, the Universal Verification Methodology (UVM) has become one of the most successful and widely used EDA standards. In addition to its...
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Whiteboard Wednesdays - Why Cadence Verification IP (VIP) is a Smart Choice...
In this week's Whiteboard Wednesdays episode, Tom Hackett discusses why over 500 customers consider Cadence Verification IP to be the S.M.A.R.T. choice when looking to verify their SoC designs.
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What's Good About ADW’s Board File Management? 16.6 Has a Few New Enhancements!
There are two new use models for PCB designers using Allegro Design Workbench (ADW) in 16.6. In 16.5, only a single PCB designer could work on the physical view of the design at one time.Now, the 16.6...
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DVCon 2014 Video: For Improved Verification, Think About the Flow
SAN JOSE, Calif.-For many years, the EDA industry thrived as myriad point tools emerged from myriad startups to address crucial electronics-design needs. Now, the increasing pace of design complexity...
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DVCon 2014: What's the Missing Piece in Verification?
SAN JOSE, Calif.-What's missing in system-design verification environments today? For many, it's software. That's the perspective of Cadence Product Director Frank Schirrmeister, who participated in a...
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Electronic Design Process Symposium (EDPS) Reviews Design Flow Challenges and...
If you want to understand how chips and systems are designed today, and what challenges lay just around the corner, there's no better place than the Electronic Design Process Symposium (EDPS) in...
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DVCon 2014: How to Close the Verification Gap
SAN JOSE, Calif.--Sometimes in the electronics industry, the best questions are at once the simplest and scariest. Consider the one raised in a DVCon 2014 panel (Richard Goering blogged in detail...
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Embedded World 2014: Silicon Labs Designs for the Internet of Things
NUREMBERG, GERMANY—Embedded World 2014 was as much about the Internet of Things (IoT) as it was about traditional automotive electronics. Silicon Labs engineers turned out to showcase a new enabling...
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Efficient Design Migration Using Virtuoso Analog Design Environment GXL
Requirements for decreased time to market, reduced silicon area, and minimized power consumption move more designs to advanced process nodes. However, redesign of circuitry is time-consuming, so it is...
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Embedded World 2014: Confronting IoT, Automotive, and Security Challenges in...
NUREMBERG, GERMANY—People don't traditionally think of big EDA companies when they stroll around big exhibitions like Embedded World. But the embedded systems engineering world today is different than...
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What's Good About DEHDL “How To” Videos? The Secret's in the 16.6 Release!
While there are several videos available for Allegro Design Entry HDL (DEHDL) in Cadence Online Support as well as in the product installation documentation folder ($CDSROOT/doc), there are times when...
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DVCon 2014 Video: HP Engineers Apply “Test Driven Development” to UVM-e
Test-driven development (TDD) and unit testing are methodologies that can greatly shorten functional verification time and increase quality. Engineers at Hewlett-Packard are currently applying these...
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Whiteboard Wednesdays—The Exploding Variety of New Interfaces for Mobile SoCs
In this week's Whiteboard Wednesdays, Tom Hackett focuses on the wide variety of new and updated mobile interfaces for mobile SoCs. These interfaces are broken down into three catagories—SoC fabric,...
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DesignCon 2014 Video: Extraction and Simulation for Simultaneous Switching Noise
Bradley Brim had a busy DesignCon 2014. Not only did the Cadence Senior Staff Product Engineer spend time demonstrating technologies in the Cadence booth and talking with customers, but he presented a...
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