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Cadence PCIe Solutions: Configurable, Compliant, and Low Power
Cadence was the first IP provider to bring PCIe Gen3 Controllers to the market. Since then, our PCIe offerings have evolved to include the lowest power PHY solutions available, FPGA platforms for...
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Whiteboard Wednesdays - Defining Different Types of USB Controllers
In this week's Whiteboard Wednesdays, Jacek Duda takes a closer look at different types of USB controllers and their roles in today's devices.
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What's in Store for the Electronics Industry in 2H 2014?
It's been a record year for the global electronics industry so far. How does the second half shape up? If you're an optimist with one eye on the coming rollout of the iPhone 6, you'd say excellent. If...
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New VIP RAKs Help in Learning Integration of Ethernet GMII and M-PCIe into...
There is always a demand for learning something simply and quickly on your own in some corner of the world. The big challenge that I have faced with learning is how to find the right learning vehicle...
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Designer View – How Emulation/Virtual Prototyping “Hybrid” Speeds Software...
200X. That's the number with which Moshe Berkovich, senior engineer at fabless semiconductor provider CSR, started a 15-minute talk that is now a recorded presentation on Cadence.com. And 200X is the...
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FinFETs, Advanced Process Nodes, and Parasitic Extraction
As use of advanced node technologies (FinFET specifically) ramp, more designers are confronting challenges in technology, productivity, and time to market. To get a sense for what engineers need to...
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Strengthen Your Plane-to-Plane Connections with Cadence 16.6 IC Package...
Manufacturability and quality of the power and ground feeds for your package are always a big concern for all of us. When you have multiple plane layers, connecting them together with reinforcing vias...
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Verification IP: 7 Things I Learned By Browsing Cadence Online Support Last...
Using proven Cadence Verification IP (VIP), you can verify SoC designs faster, more thoroughly, and with less effort. While innovating and providing great products and technologies, the VIP team at...
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Voltus-Fi Custom Power Integrity Solution: Electromigration and IR Drop at...
Power signoff isn't just about digital logic—analog and custom digital blocks in SoCs need power integrity analysis as well. That's why Cadence today (Aug. 4, 2014) is introducing the Voltus-Fi Custom...
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New OrCAD Offerings Zero in on Engineering Productivity Challenges
In the fast-paced, ever-changing world of electronics design, we attack the big challenges relentlessly. But it's the "little things" that can add up quickly and kill design team productivity if we...
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Whiteboard Wednesdays - The Evolution of NAND Flash
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Disk Drive’s Days Might be Numbered: Woz
SANTA CLARA, Calif.--Apple cofounder Steve Wozniak can envision the end of hard disk drives, replaced by solid-state memories. "I'm a purist, I'd love to see hard disks go away," he said during a...
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Flash Memory Summit: 3D NAND Flash Faces Cost, Reliability Challenges
3D NAND Flash architectures will provide the best option for increasing storage densities in future years, according to panelists at a plenary session at the Flash Memory Summit Aug. 5, 2014. But given...
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Boost Efficiency and Performance of Simulation Acceleration Through New Rapid...
The state-of-the-art Palladium XP hardware/software verification computing platform unifies best-in-class acceleration and emulation capabilities in a single environment to boost verification...
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Q&A: Kathryn Kranen Discusses Jasper, Formal Verification, and the Cadence...
Few individuals have been as visible and influential in the EDA industry as Kathryn Kranen, CEO of formal verification pioneer Jasper Design Automation until its acquisition by Cadence in June 2014....
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FinFET, Advanced Nodes, and MIPI Top Most-Read List
To get a sense for what's driving electronics engineers in 2014, look no farther than Cadence's blogs: So far this year, stories about FinFETs, advanced-node availability and certification, how to...
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What's Good About Allegro DEHDL Net Renaming? The Secret's in the 16.6 Release!
Just a brief post this week to mention a new capability for Allegro Design Entry HDL (DEHDL) that was made available in the 16.6-QIR4 release.You can now employ net renaming without loss of data:All...
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Whiteboard Wednesdays - How to Support Higher Performance Multimedia...
In this week's Whiteboard Wednesdays, Charles Qi continues his discussion on hosted virtual desktop applications, explaining how a growing number of users are increasing the demand for higher...
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Designer View – RTL Synthesis Success Strategies at 28nm and Below
RTL synthesis is not a simple pushbutton tool, especially at 28nm and below. In a recorded presentation at the Cadence web site Ramesh Rajagopalan, chip lead for physical implementation of networking...
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Flash Memory Summit: A New Approach to Storage Processing
SANTA CLARA, Calif.—The promise of flash memory storage systems—despite robust market success in recent years—has yet to be realized. And the unique technical challenges and changing market...
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